Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T3,T5

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11505297	12577	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11505297	116003	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11505297	6816992	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11505297	185542	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11505297	12577	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11505297	116003	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11505297	6816992	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11505297	185542	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	12577	0	0
T3	37174	73	0	0
T4	10226	0	0	0
T5	26056	75	0	0
T6	2218	4	0	0
T7	348007	304	0	0
T8	2254	14	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	75	0	0
T12	3605	13	0	0
T13	0	4	0	0
T14	0	7	0	0
T25	0	29	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	116003	0	0
T3	37174	674	0	0
T4	10226	0	0	0
T5	26056	704	0	0
T6	2218	37	0	0
T7	348007	2743	0	0
T8	2254	126	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	719	0	0
T12	3605	117	0	0
T13	0	38	0	0
T14	0	63	0	0
T25	0	264	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	6816992	0	0
T1	1228	657	0	0
T2	5502	568	0	0
T3	37174	18927	0	0
T4	10226	9659	0	0
T5	26056	8739	0	0
T6	2218	1242	0	0
T7	348007	273262	0	0
T8	2254	1417	0	0
T9	5466	565	0	0
T10	2101	917	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	185542	0	0
T3	37174	1052	0	0
T4	10226	0	0	0
T5	26056	1133	0	0
T6	2218	61	0	0
T7	348007	4345	0	0
T8	2254	209	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	1121	0	0
T12	3605	185	0	0
T13	0	64	0	0
T14	0	102	0	0
T25	0	415	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	12577	0	0
T3	37174	73	0	0
T4	10226	0	0	0
T5	26056	75	0	0
T6	2218	4	0	0
T7	348007	304	0	0
T8	2254	14	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	75	0	0
T12	3605	13	0	0
T13	0	4	0	0
T14	0	7	0	0
T25	0	29	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	116003	0	0
T3	37174	674	0	0
T4	10226	0	0	0
T5	26056	704	0	0
T6	2218	37	0	0
T7	348007	2743	0	0
T8	2254	126	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	719	0	0
T12	3605	117	0	0
T13	0	38	0	0
T14	0	63	0	0
T25	0	264	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	6816992	0	0
T1	1228	657	0	0
T2	5502	568	0	0
T3	37174	18927	0	0
T4	10226	9659	0	0
T5	26056	8739	0	0
T6	2218	1242	0	0
T7	348007	273262	0	0
T8	2254	1417	0	0
T9	5466	565	0	0
T10	2101	917	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	185542	0	0
T3	37174	1052	0	0
T4	10226	0	0	0
T5	26056	1133	0	0
T6	2218	61	0	0
T7	348007	4345	0	0
T8	2254	209	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	1121	0	0
T12	3605	185	0	0
T13	0	64	0	0
T14	0	102	0	0
T25	0	415	0	0