Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T7,T25
1	0	Covered	T3,T7,T25

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	53776805	8569	0	0
CascadeEffAonToRstPorAboveRise_A	53776805	8569	0	0
CascadeEffAonToRstPorIoAboveFall_A	51624079	8569	0	0
CascadeEffAonToRstPorIoAboveRise_A	51624079	8569	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25813013	8569	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25813013	8569	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12906044	8569	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12906044	8569	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25812948	8569	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25812948	8569	0	0
CascadeLcToLcAboveFall_A	53776805	21146	0	0
CascadeLcToLcAboveRise_A	53776805	21146	0	0
CascadeLcToLcAonAboveFall_A	1628738	21146	0	0
CascadeLcToLcAonAboveRise_A	1628738	21146	0	0
CascadeLcToLcShadowedAboveFall_A	53776805	21146	0	0
CascadeLcToLcShadowedAboveRise_A	53776805	21146	0	0
CascadePorToAonAboveFall_A	1628738	6896	0	0
CascadeSysToSysAboveFall_A	53776805	21146	0	0
CascadeSysToSysAboveRise_A	53776805	21146	0	0
ScanRstToAonRise_A	1628738	195	0	0
StablePorToAonRise_A	1628738	8569	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11505297	21146	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11505297	21146	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11505297	21146	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11505297	21146	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12906044	21146	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12906044	21146	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11505297	21146	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11505297	21146	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11505297	21146	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11505297	21146	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53776805	8569	0	0
T1	5498	1	0	0
T2	24408	8	0	0
T3	195485	40	0	0
T4	42993	1	0	0
T5	121708	27	0	0
T6	10641	2	0	0
T7	161950	161	0	0
T8	13672	1	0	0
T9	24253	8	0	0
T10	9134	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53776805	8569	0	0
T1	5498	1	0	0
T2	24408	8	0	0
T3	195485	40	0	0
T4	42993	1	0	0
T5	121708	27	0	0
T6	10641	2	0	0
T7	161950	161	0	0
T8	13672	1	0	0
T9	24253	8	0	0
T10	9134	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51624079	8569	0	0
T1	5278	1	0	0
T2	23424	8	0	0
T3	187643	40	0	0
T4	41271	1	0	0
T5	116805	27	0	0
T6	10216	2	0	0
T7	155468	161	0	0
T8	13123	1	0	0
T9	23282	8	0	0
T10	8769	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51624079	8569	0	0
T1	5278	1	0	0
T2	23424	8	0	0
T3	187643	40	0	0
T4	41271	1	0	0
T5	116805	27	0	0
T6	10216	2	0	0
T7	155468	161	0	0
T8	13123	1	0	0
T9	23282	8	0	0
T10	8769	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25813013	8569	0	0
T1	2638	1	0	0
T2	11709	8	0	0
T3	93828	40	0	0
T4	20636	1	0	0
T5	58408	27	0	0
T6	5108	2	0	0
T7	777401	161	0	0
T8	6562	1	0	0
T9	11635	8	0	0
T10	4384	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25813013	8569	0	0
T1	2638	1	0	0
T2	11709	8	0	0
T3	93828	40	0	0
T4	20636	1	0	0
T5	58408	27	0	0
T6	5108	2	0	0
T7	777401	161	0	0
T8	6562	1	0	0
T9	11635	8	0	0
T10	4384	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	8569	0	0
T1	1318	1	0	0
T2	5857	8	0	0
T3	46909	40	0	0
T4	10318	1	0	0
T5	29205	27	0	0
T6	2552	2	0	0
T7	388698	161	0	0
T8	3280	1	0	0
T9	5818	8	0	0
T10	2191	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	8569	0	0
T1	1318	1	0	0
T2	5857	8	0	0
T3	46909	40	0	0
T4	10318	1	0	0
T5	29205	27	0	0
T6	2552	2	0	0
T7	388698	161	0	0
T8	3280	1	0	0
T9	5818	8	0	0
T10	2191	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25812948	8569	0	0
T1	2638	1	0	0
T2	11719	8	0	0
T3	93807	40	0	0
T4	20637	1	0	0
T5	58418	27	0	0
T6	5106	2	0	0
T7	777423	161	0	0
T8	6563	1	0	0
T9	11643	8	0	0
T10	4384	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25812948	8569	0	0
T1	2638	1	0	0
T2	11719	8	0	0
T3	93807	40	0	0
T4	20637	1	0	0
T5	58418	27	0	0
T6	5106	2	0	0
T7	777423	161	0	0
T8	6563	1	0	0
T9	11643	8	0	0
T10	4384	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53776805	21146	0	0
T1	5498	1	0	0
T2	24408	8	0	0
T3	195485	113	0	0
T4	42993	1	0	0
T5	121708	102	0	0
T6	10641	6	0	0
T7	161950	465	0	0
T8	13672	15	0	0
T9	24253	8	0	0
T10	9134	2	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53776805	21146	0	0
T1	5498	1	0	0
T2	24408	8	0	0
T3	195485	113	0	0
T4	42993	1	0	0
T5	121708	102	0	0
T6	10641	6	0	0
T7	161950	465	0	0
T8	13672	15	0	0
T9	24253	8	0	0
T10	9134	2	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628738	21146	0	0
T1	164	1	0	0
T2	733	8	0	0
T3	5995	113	0	0
T4	1289	1	0	0
T5	3666	102	0	0
T6	317	6	0	0
T7	49235	465	0	0
T8	408	15	0	0
T9	729	8	0	0
T10	272	2	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628738	21146	0	0
T1	164	1	0	0
T2	733	8	0	0
T3	5995	113	0	0
T4	1289	1	0	0
T5	3666	102	0	0
T6	317	6	0	0
T7	49235	465	0	0
T8	408	15	0	0
T9	729	8	0	0
T10	272	2	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53776805	21146	0	0
T1	5498	1	0	0
T2	24408	8	0	0
T3	195485	113	0	0
T4	42993	1	0	0
T5	121708	102	0	0
T6	10641	6	0	0
T7	161950	465	0	0
T8	13672	15	0	0
T9	24253	8	0	0
T10	9134	2	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53776805	21146	0	0
T1	5498	1	0	0
T2	24408	8	0	0
T3	195485	113	0	0
T4	42993	1	0	0
T5	121708	102	0	0
T6	10641	6	0	0
T7	161950	465	0	0
T8	13672	15	0	0
T9	24253	8	0	0
T10	9134	2	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628738	6896	0	0
T1	164	1	0	0
T2	733	8	0	0
T3	5995	21	0	0
T4	1289	1	0	0
T5	3666	27	0	0
T6	317	1	0	0
T7	49235	89	0	0
T8	408	1	0	0
T9	729	8	0	0
T10	272	2	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53776805	21146	0	0
T1	5498	1	0	0
T2	24408	8	0	0
T3	195485	113	0	0
T4	42993	1	0	0
T5	121708	102	0	0
T6	10641	6	0	0
T7	161950	465	0	0
T8	13672	15	0	0
T9	24253	8	0	0
T10	9134	2	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53776805	21146	0	0
T1	5498	1	0	0
T2	24408	8	0	0
T3	195485	113	0	0
T4	42993	1	0	0
T5	121708	102	0	0
T6	10641	6	0	0
T7	161950	465	0	0
T8	13672	15	0	0
T9	24253	8	0	0
T10	9134	2	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628738	195	0	0
T3	5995	4	0	0
T4	1289	0	0	0
T5	3666	0	0	0
T6	317	0	0	0
T7	49235	7	0	0
T8	408	0	0	0
T9	729	0	0	0
T10	272	0	0	0
T11	7084	0	0	0
T12	570	0	0	0
T25	0	1	0	0
T38	0	1	0	0
T47	0	1	0	0
T110	0	2	0	0
T115	0	3	0	0
T116	0	4	0	0
T117	0	1	0	0
T143	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628738	8569	0	0
T1	164	1	0	0
T2	733	8	0	0
T3	5995	40	0	0
T4	1289	1	0	0
T5	3666	27	0	0
T6	317	2	0	0
T7	49235	161	0	0
T8	408	1	0	0
T9	729	8	0	0
T10	272	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	21146	0	0
T1	1228	1	0	0
T2	5502	8	0	0
T3	37174	113	0	0
T4	10226	1	0	0
T5	26056	102	0	0
T6	2218	6	0	0
T7	348007	465	0	0
T8	2254	15	0	0
T9	5466	8	0	0
T10	2101	2	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	21146	0	0
T1	1228	1	0	0
T2	5502	8	0	0
T3	37174	113	0	0
T4	10226	1	0	0
T5	26056	102	0	0
T6	2218	6	0	0
T7	348007	465	0	0
T8	2254	15	0	0
T9	5466	8	0	0
T10	2101	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	21146	0	0
T1	1228	1	0	0
T2	5502	8	0	0
T3	37174	113	0	0
T4	10226	1	0	0
T5	26056	102	0	0
T6	2218	6	0	0
T7	348007	465	0	0
T8	2254	15	0	0
T9	5466	8	0	0
T10	2101	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	21146	0	0
T1	1228	1	0	0
T2	5502	8	0	0
T3	37174	113	0	0
T4	10226	1	0	0
T5	26056	102	0	0
T6	2218	6	0	0
T7	348007	465	0	0
T8	2254	15	0	0
T9	5466	8	0	0
T10	2101	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	21146	0	0
T1	1318	1	0	0
T2	5857	8	0	0
T3	46909	113	0	0
T4	10318	1	0	0
T5	29205	102	0	0
T6	2552	6	0	0
T7	388698	465	0	0
T8	3280	15	0	0
T9	5818	8	0	0
T10	2191	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	21146	0	0
T1	1318	1	0	0
T2	5857	8	0	0
T3	46909	113	0	0
T4	10318	1	0	0
T5	29205	102	0	0
T6	2552	6	0	0
T7	388698	465	0	0
T8	3280	15	0	0
T9	5818	8	0	0
T10	2191	2	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	21146	0	0
T1	1228	1	0	0
T2	5502	8	0	0
T3	37174	113	0	0
T4	10226	1	0	0
T5	26056	102	0	0
T6	2218	6	0	0
T7	348007	465	0	0
T8	2254	15	0	0
T9	5466	8	0	0
T10	2101	2	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	21146	0	0
T1	1228	1	0	0
T2	5502	8	0	0
T3	37174	113	0	0
T4	10226	1	0	0
T5	26056	102	0	0
T6	2218	6	0	0
T7	348007	465	0	0
T8	2254	15	0	0
T9	5466	8	0	0
T10	2101	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	21146	0	0
T1	1228	1	0	0
T2	5502	8	0	0
T3	37174	113	0	0
T4	10226	1	0	0
T5	26056	102	0	0
T6	2218	6	0	0
T7	348007	465	0	0
T8	2254	15	0	0
T9	5466	8	0	0
T10	2101	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11505297	21146	0	0
T1	1228	1	0	0
T2	5502	8	0	0
T3	37174	113	0	0
T4	10226	1	0	0
T5	26056	102	0	0
T6	2218	6	0	0
T7	348007	465	0	0
T8	2254	15	0	0
T9	5466	8	0	0
T10	2101	2	0	0