Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	638316	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

387167

1

T1

1119

T2

3

T3

1067

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	548728	1			T1	1500		T3	1622		T4	10385
values[0x0]	237683	1			T1	864		T2	7		T3	619
values[0x1]	239072	1			T1	836		T2	1		T3	644

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	535752	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

489731

1

T1

1428

T2

3

T3

1390

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3881	1			T1	12		T4	60		T5	86
valid_sources[0x01]	5660	1			T1	10		T4	100		T5	102
valid_sources[0x02]	3557	1			T1	20		T2	1		T4	77
valid_sources[0x03]	7599	1			T1	13		T3	6		T4	64
valid_sources[0x04]	3518	1			T1	10		T4	56		T5	62
valid_sources[0x05]	3616	1			T1	15		T4	54		T5	83
valid_sources[0x06]	4194	1			T1	17		T4	71		T5	89
valid_sources[0x07]	3929	1			T1	13		T4	73		T5	83
valid_sources[0x08]	3982	1			T1	13		T4	67		T5	81
valid_sources[0x09]	7956	1			T1	14		T4	71		T5	73
valid_sources[0x0a]	3509	1			T1	10		T4	61		T5	105
valid_sources[0x0b]	3508	1			T1	14		T3	1		T4	73
valid_sources[0x0c]	3342	1			T1	12		T4	124		T5	75
valid_sources[0x0d]	6457	1			T1	9		T4	81		T5	74
valid_sources[0x0e]	3476	1			T1	8		T4	71		T5	99
valid_sources[0x0f]	3972	1			T1	14		T4	68		T5	99
valid_sources[0x10]	5340	1			T1	13		T3	282		T4	61
valid_sources[0x11]	3530	1			T1	16		T4	77		T5	97
valid_sources[0x12]	3814	1			T1	8		T3	1		T4	80
valid_sources[0x13]	4775	1			T1	17		T4	90		T5	79
valid_sources[0x14]	3464	1			T1	11		T4	76		T5	93
valid_sources[0x15]	3260	1			T1	9		T4	81		T5	72
valid_sources[0x16]	3999	1			T1	15		T4	62		T5	86
valid_sources[0x17]	3829	1			T1	13		T4	69		T5	66
valid_sources[0x18]	3786	1			T1	17		T4	76		T5	89
valid_sources[0x19]	4092	1			T1	13		T4	86		T5	67
valid_sources[0x1a]	3597	1			T1	9		T4	65		T5	80
valid_sources[0x1b]	4206	1			T1	17		T3	69		T4	66
valid_sources[0x1c]	3074	1			T1	6		T4	60		T5	73
valid_sources[0x1d]	3351	1			T1	10		T4	61		T5	85
valid_sources[0x1e]	4695	1			T1	11		T4	73		T5	78
valid_sources[0x1f]	3284	1			T1	11		T4	62		T5	100
valid_sources[0x20]	3975	1			T1	15		T3	113		T4	65
valid_sources[0x21]	3113	1			T1	13		T4	73		T5	66
valid_sources[0x22]	3587	1			T1	11		T3	2		T4	76
valid_sources[0x23]	3439	1			T1	7		T4	88		T5	97
valid_sources[0x24]	4056	1			T1	12		T4	70		T5	74
valid_sources[0x25]	3975	1			T1	16		T4	69		T5	71
valid_sources[0x26]	3872	1			T1	12		T4	69		T5	69
valid_sources[0x27]	4211	1			T1	11		T4	63		T5	78
valid_sources[0x28]	3699	1			T1	18		T3	1		T4	75
valid_sources[0x29]	3119	1			T1	14		T4	47		T5	92
valid_sources[0x2a]	3582	1			T1	7		T4	70		T5	89
valid_sources[0x2b]	7255	1			T1	11		T4	90		T5	78
valid_sources[0x2c]	3629	1			T1	13		T4	75		T5	108
valid_sources[0x2d]	3400	1			T1	13		T4	65		T5	91
valid_sources[0x2e]	3551	1			T1	14		T3	1		T4	74
valid_sources[0x2f]	3716	1			T1	16		T4	79		T5	58
valid_sources[0x30]	3707	1			T1	12		T4	73		T5	80
valid_sources[0x31]	3245	1			T1	9		T4	99		T5	96
valid_sources[0x32]	4048	1			T1	5		T3	58		T4	71
valid_sources[0x33]	3884	1			T1	15		T4	63		T5	75
valid_sources[0x34]	3120	1			T1	10		T4	70		T5	72
valid_sources[0x35]	3581	1			T1	14		T4	60		T5	65
valid_sources[0x36]	4738	1			T1	7		T4	57		T5	75
valid_sources[0x37]	3972	1			T1	19		T4	77		T5	67
valid_sources[0x38]	7247	1			T1	12		T4	45		T5	63
valid_sources[0x39]	4403	1			T1	12		T4	65		T5	83
valid_sources[0x3a]	4046	1			T1	13		T4	85		T5	80
valid_sources[0x3b]	4074	1			T1	13		T3	4		T4	60
valid_sources[0x3c]	4170	1			T1	15		T4	69		T5	84
valid_sources[0x3d]	3920	1			T1	10		T4	83		T5	76
valid_sources[0x3e]	3511	1			T1	13		T4	75		T5	81
valid_sources[0x3f]	3399	1			T1	8		T4	91		T5	54
valid_sources[0x40]	4255	1			T1	16		T4	71		T5	111
valid_sources[0x41]	4581	1			T1	10		T4	61		T5	60
valid_sources[0x42]	5751	1			T1	15		T4	99		T5	89
valid_sources[0x43]	4198	1			T1	13		T4	83		T5	90
valid_sources[0x44]	4021	1			T1	9		T4	87		T5	79
valid_sources[0x45]	3806	1			T1	8		T4	54		T5	91
valid_sources[0x46]	6551	1			T1	14		T3	1		T4	68
valid_sources[0x47]	4022	1			T1	13		T4	75		T5	88
valid_sources[0x48]	3759	1			T1	16		T4	89		T5	79
valid_sources[0x49]	3470	1			T1	10		T4	67		T5	45
valid_sources[0x4a]	8107	1			T1	10		T4	74		T5	111
valid_sources[0x4b]	3344	1			T1	9		T4	74		T5	66
valid_sources[0x4c]	4178	1			T1	7		T4	76		T5	84
valid_sources[0x4d]	3714	1			T1	17		T4	55		T5	95
valid_sources[0x4e]	3532	1			T1	9		T4	72		T5	83
valid_sources[0x4f]	4769	1			T1	14		T4	51		T5	95
valid_sources[0x50]	3991	1			T1	14		T4	59		T5	120
valid_sources[0x51]	4963	1			T1	18		T4	80		T5	68
valid_sources[0x52]	3733	1			T1	12		T4	62		T5	58
valid_sources[0x53]	4329	1			T1	7		T4	53		T5	62
valid_sources[0x54]	3510	1			T1	7		T2	2		T4	86
valid_sources[0x55]	4174	1			T1	17		T4	69		T5	76
valid_sources[0x56]	3874	1			T1	9		T4	82		T5	93
valid_sources[0x57]	4048	1			T1	7		T4	69		T5	90
valid_sources[0x58]	4642	1			T1	8		T4	57		T5	68
valid_sources[0x59]	3872	1			T1	12		T4	70		T5	90
valid_sources[0x5a]	5515	1			T1	18		T4	71		T5	82
valid_sources[0x5b]	4701	1			T1	9		T4	73		T5	72
valid_sources[0x5c]	3408	1			T1	12		T4	74		T5	86
valid_sources[0x5d]	3888	1			T1	11		T4	65		T5	66
valid_sources[0x5e]	3421	1			T1	13		T4	69		T5	71
valid_sources[0x5f]	4533	1			T1	15		T4	94		T5	59
valid_sources[0x60]	3903	1			T1	13		T4	54		T5	102
valid_sources[0x61]	4186	1			T1	4		T4	72		T5	76
valid_sources[0x62]	3404	1			T1	11		T4	76		T5	78
valid_sources[0x63]	4503	1			T1	17		T3	1		T4	55
valid_sources[0x64]	3242	1			T1	11		T4	72		T5	100
valid_sources[0x65]	3255	1			T1	14		T4	76		T5	93
valid_sources[0x66]	3819	1			T1	8		T4	61		T5	72
valid_sources[0x67]	3569	1			T1	11		T4	73		T5	99
valid_sources[0x68]	4071	1			T1	13		T4	79		T5	74
valid_sources[0x69]	3357	1			T1	10		T4	85		T5	72
valid_sources[0x6a]	3837	1			T1	13		T4	80		T5	92
valid_sources[0x6b]	4043	1			T1	11		T4	50		T5	106
valid_sources[0x6c]	4411	1			T1	14		T4	73		T5	95
valid_sources[0x6d]	3297	1			T1	9		T4	78		T5	74
valid_sources[0x6e]	3639	1			T1	14		T4	58		T5	106
valid_sources[0x6f]	4669	1			T1	10		T4	78		T5	82
valid_sources[0x70]	4037	1			T1	14		T4	75		T5	95
valid_sources[0x71]	5124	1			T1	13		T4	88		T5	60
valid_sources[0x72]	3851	1			T1	13		T4	70		T5	64
valid_sources[0x73]	3826	1			T1	13		T4	60		T5	54
valid_sources[0x74]	4082	1			T1	14		T4	69		T5	86
valid_sources[0x75]	3850	1			T1	16		T4	52		T5	74
valid_sources[0x76]	4247	1			T1	11		T4	55		T5	62
valid_sources[0x77]	3467	1			T1	9		T4	104		T5	53
valid_sources[0x78]	5147	1			T1	11		T4	89		T5	73
valid_sources[0x79]	3740	1			T1	11		T4	86		T5	67
valid_sources[0x7a]	3303	1			T1	12		T4	81		T5	85
valid_sources[0x7b]	3312	1			T1	15		T4	78		T5	69
valid_sources[0x7c]	3716	1			T1	24		T4	66		T5	64
valid_sources[0x7d]	3499	1			T1	13		T4	62		T5	74
valid_sources[0x7e]	3937	1			T1	9		T3	5		T4	78
valid_sources[0x7f]	3197	1			T1	14		T4	46		T5	92
valid_sources[0x80]	3780	1			T1	8		T4	64		T5	96

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

258437

1

T1

681

T3

745

T4

4845

values[0x0]

all_enables

biggest_size

83552

1

T1

284

T2

3

T3

208

values[0x1]

all_enables

biggest_size

45178

1

T1

154

T3

114

T4

675