Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T10
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T10
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T10
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T10
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T10
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T10
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13743217	14387	0	0
gen_assertions[0].RstEnOn_A	13743217	1078	0	0
gen_assertions[0].RstNOff_A	13743217	14387	0	0
gen_assertions[0].RstNOn_A	13743217	1078	0	0
gen_assertions[1].RstEnOff_A	54971793	13048	0	0
gen_assertions[1].RstEnOn_A	54971793	1060	0	0
gen_assertions[1].RstNOff_A	54971793	13048	0	0
gen_assertions[1].RstNOn_A	54971793	1060	0	0
gen_assertions[2].RstEnOff_A	27486797	13110	0	0
gen_assertions[2].RstEnOn_A	27486797	1056	0	0
gen_assertions[2].RstNOff_A	27486797	13110	0	0
gen_assertions[2].RstNOn_A	27486797	1056	0	0
gen_assertions[3].RstEnOff_A	27486607	13162	0	0
gen_assertions[3].RstEnOn_A	27486607	1103	0	0
gen_assertions[3].RstNOff_A	27486607	13162	0	0
gen_assertions[3].RstNOn_A	27486607	1103	0	0
gen_assertions[4].RstEnOff_A	1735563	22877	0	0
gen_assertions[4].RstEnOn_A	1735563	1169	0	0
gen_assertions[4].RstNOff_A	1735563	22877	0	0
gen_assertions[4].RstNOn_A	1735563	1169	0	0
gen_assertions[5].RstEnOff_A	13743217	14637	0	0
gen_assertions[5].RstEnOn_A	13743217	1206	0	0
gen_assertions[5].RstNOff_A	13743217	14637	0	0
gen_assertions[5].RstNOn_A	13743217	1206	0	0
gen_assertions[6].RstEnOff_A	13743217	14692	0	0
gen_assertions[6].RstEnOn_A	13743217	1259	0	0
gen_assertions[6].RstNOff_A	13743217	14692	0	0
gen_assertions[6].RstNOn_A	13743217	1259	0	0
gen_assertions[7].RstEnOff_A	13743217	14721	0	0
gen_assertions[7].RstEnOn_A	13743217	1298	0	0
gen_assertions[7].RstNOff_A	13743217	14721	0	0
gen_assertions[7].RstNOn_A	13743217	1298	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	14387	0	0
T1	29255	75	0	0
T2	1452	0	0	0
T3	45091	37	0	0
T4	235646	228	0	0
T5	254002	270	0	0
T6	5294	0	0	0
T7	4519	5	0	0
T8	1998	0	0	0
T9	45187	75	0	0
T10	134409	160	0	0
T11	0	220	0	0
T12	0	8	0	0
T22	0	2	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	1078	0	0
T4	235646	9	0	0
T5	254002	12	0	0
T6	5294	0	0	0
T7	4519	1	0	0
T8	1998	0	0	0
T9	45187	0	0	0
T10	134409	33	0	0
T11	186421	48	0	0
T12	3127	2	0	0
T22	1707	0	0	0
T36	0	6	0	0
T38	0	1	0	0
T39	0	1	0	0
T54	0	5	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	14387	0	0
T1	29255	75	0	0
T2	1452	0	0	0
T3	45091	37	0	0
T4	235646	228	0	0
T5	254002	270	0	0
T6	5294	0	0	0
T7	4519	5	0	0
T8	1998	0	0	0
T9	45187	75	0	0
T10	134409	160	0	0
T11	0	220	0	0
T12	0	8	0	0
T22	0	2	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	1078	0	0
T4	235646	9	0	0
T5	254002	12	0	0
T6	5294	0	0	0
T7	4519	1	0	0
T8	1998	0	0	0
T9	45187	0	0	0
T10	134409	33	0	0
T11	186421	48	0	0
T12	3127	2	0	0
T22	1707	0	0	0
T36	0	6	0	0
T38	0	1	0	0
T39	0	1	0	0
T54	0	5	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54971793	13048	0	0
T1	117030	63	0	0
T2	5816	0	0	0
T3	180368	35	0	0
T4	942462	207	0	0
T5	101586	236	0	0
T6	21177	0	0	0
T7	18085	4	0	0
T8	7997	0	0	0
T9	180736	72	0	0
T10	537599	142	0	0
T11	0	194	0	0
T12	0	8	0	0
T22	0	2	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54971793	1060	0	0
T4	942462	13	0	0
T5	101586	8	0	0
T6	21177	0	0	0
T7	18085	1	0	0
T8	7997	0	0	0
T9	180736	0	0	0
T10	537599	28	0	0
T11	745643	46	0	0
T12	12512	0	0	0
T22	6834	1	0	0
T36	0	7	0	0
T39	0	1	0	0
T54	0	6	0	0
T55	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54971793	13048	0	0
T1	117030	63	0	0
T2	5816	0	0	0
T3	180368	35	0	0
T4	942462	207	0	0
T5	101586	236	0	0
T6	21177	0	0	0
T7	18085	4	0	0
T8	7997	0	0	0
T9	180736	72	0	0
T10	537599	142	0	0
T11	0	194	0	0
T12	0	8	0	0
T22	0	2	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54971793	1060	0	0
T4	942462	13	0	0
T5	101586	8	0	0
T6	21177	0	0	0
T7	18085	1	0	0
T8	7997	0	0	0
T9	180736	0	0	0
T10	537599	28	0	0
T11	745643	46	0	0
T12	12512	0	0	0
T22	6834	1	0	0
T36	0	7	0	0
T39	0	1	0	0
T54	0	6	0	0
T55	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27486797	13110	0	0
T1	58512	63	0	0
T2	2907	0	0	0
T3	90185	35	0	0
T4	471278	209	0	0
T5	507996	240	0	0
T6	10589	0	0	0
T7	9042	3	0	0
T8	3998	0	0	0
T9	90377	72	0	0
T10	268822	149	0	0
T11	0	197	0	0
T12	0	8	0	0
T22	0	2	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27486797	1056	0	0
T4	471278	15	0	0
T5	507996	11	0	0
T6	10589	0	0	0
T7	9042	0	0	0
T8	3998	0	0	0
T9	90377	0	0	0
T10	268822	36	0	0
T11	372841	50	0	0
T12	6256	0	0	0
T22	3417	0	0	0
T36	0	11	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	3	0	0
T54	0	8	0	0
T94	0	9	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27486797	13110	0	0
T1	58512	63	0	0
T2	2907	0	0	0
T3	90185	35	0	0
T4	471278	209	0	0
T5	507996	240	0	0
T6	10589	0	0	0
T7	9042	3	0	0
T8	3998	0	0	0
T9	90377	72	0	0
T10	268822	149	0	0
T11	0	197	0	0
T12	0	8	0	0
T22	0	2	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27486797	1056	0	0
T4	471278	15	0	0
T5	507996	11	0	0
T6	10589	0	0	0
T7	9042	0	0	0
T8	3998	0	0	0
T9	90377	0	0	0
T10	268822	36	0	0
T11	372841	50	0	0
T12	6256	0	0	0
T22	3417	0	0	0
T36	0	11	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	3	0	0
T54	0	8	0	0
T94	0	9	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27486607	13162	0	0
T1	58496	63	0	0
T2	2908	0	0	0
T3	90192	35	0	0
T4	471260	207	0	0
T5	507986	238	0	0
T6	10589	0	0	0
T7	9042	3	0	0
T8	3998	0	0	0
T9	90361	72	0	0
T10	268820	154	0	0
T11	0	200	0	0
T12	0	8	0	0
T22	0	2	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27486607	1103	0	0
T4	471260	13	0	0
T5	507986	9	0	0
T6	10589	0	0	0
T7	9042	0	0	0
T8	3998	0	0	0
T9	90361	0	0	0
T10	268820	40	0	0
T11	372822	51	0	0
T12	6255	0	0	0
T22	3417	0	0	0
T36	0	10	0	0
T38	0	1	0	0
T42	0	5	0	0
T54	0	8	0	0
T55	0	1	0	0
T94	0	15	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27486607	13162	0	0
T1	58496	63	0	0
T2	2908	0	0	0
T3	90192	35	0	0
T4	471260	207	0	0
T5	507986	238	0	0
T6	10589	0	0	0
T7	9042	3	0	0
T8	3998	0	0	0
T9	90361	72	0	0
T10	268820	154	0	0
T11	0	200	0	0
T12	0	8	0	0
T22	0	2	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27486607	1103	0	0
T4	471260	13	0	0
T5	507986	9	0	0
T6	10589	0	0	0
T7	9042	0	0	0
T8	3998	0	0	0
T9	90361	0	0	0
T10	268820	40	0	0
T11	372822	51	0	0
T12	6255	0	0	0
T22	3417	0	0	0
T36	0	10	0	0
T38	0	1	0	0
T42	0	5	0	0
T54	0	8	0	0
T55	0	1	0	0
T94	0	15	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1735563	22877	0	0
T1	3670	76	0	0
T2	180	1	0	0
T3	5715	56	0	0
T4	29971	360	0	0
T5	32300	401	0	0
T6	659	2	0	0
T7	564	6	0	0
T8	249	1	0	0
T9	5664	86	0	0
T10	17051	219	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1735563	1169	0	0
T4	29971	15	0	0
T5	32300	9	0	0
T6	659	0	0	0
T7	564	0	0	0
T8	249	0	0	0
T9	5664	0	0	0
T10	17051	34	0	0
T11	23621	50	0	0
T12	390	0	0	0
T22	213	0	0	0
T36	0	12	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	7	0	0
T54	0	8	0	0
T94	0	15	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1735563	22877	0	0
T1	3670	76	0	0
T2	180	1	0	0
T3	5715	56	0	0
T4	29971	360	0	0
T5	32300	401	0	0
T6	659	2	0	0
T7	564	6	0	0
T8	249	1	0	0
T9	5664	86	0	0
T10	17051	219	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1735563	1169	0	0
T4	29971	15	0	0
T5	32300	9	0	0
T6	659	0	0	0
T7	564	0	0	0
T8	249	0	0	0
T9	5664	0	0	0
T10	17051	34	0	0
T11	23621	50	0	0
T12	390	0	0	0
T22	213	0	0	0
T36	0	12	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	7	0	0
T54	0	8	0	0
T94	0	15	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	14637	0	0
T1	29255	75	0	0
T2	1452	0	0	0
T3	45091	37	0	0
T4	235646	231	0	0
T5	254002	270	0	0
T6	5294	0	0	0
T7	4519	4	0	0
T8	1998	0	0	0
T9	45187	75	0	0
T10	134409	166	0	0
T11	0	213	0	0
T12	0	8	0	0
T22	0	2	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	1206	0	0
T4	235646	13	0	0
T5	254002	11	0	0
T6	5294	0	0	0
T7	4519	0	0	0
T8	1998	0	0	0
T9	45187	0	0	0
T10	134409	38	0	0
T11	186421	41	0	0
T12	3127	0	0	0
T22	1707	0	0	0
T36	0	12	0	0
T42	0	4	0	0
T54	0	9	0	0
T60	0	9	0	0
T94	0	15	0	0
T95	0	8	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	14637	0	0
T1	29255	75	0	0
T2	1452	0	0	0
T3	45091	37	0	0
T4	235646	231	0	0
T5	254002	270	0	0
T6	5294	0	0	0
T7	4519	4	0	0
T8	1998	0	0	0
T9	45187	75	0	0
T10	134409	166	0	0
T11	0	213	0	0
T12	0	8	0	0
T22	0	2	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	1206	0	0
T4	235646	13	0	0
T5	254002	11	0	0
T6	5294	0	0	0
T7	4519	0	0	0
T8	1998	0	0	0
T9	45187	0	0	0
T10	134409	38	0	0
T11	186421	41	0	0
T12	3127	0	0	0
T22	1707	0	0	0
T36	0	12	0	0
T42	0	4	0	0
T54	0	9	0	0
T60	0	9	0	0
T94	0	15	0	0
T95	0	8	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	14692	0	0
T1	29255	75	0	0
T2	1452	0	0	0
T3	45091	37	0	0
T4	235646	229	0	0
T5	254002	269	0	0
T6	5294	0	0	0
T7	4519	4	0	0
T8	1998	0	0	0
T9	45187	75	0	0
T10	134409	165	0	0
T11	0	223	0	0
T12	0	8	0	0
T22	0	2	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	1259	0	0
T4	235646	10	0	0
T5	254002	10	0	0
T6	5294	0	0	0
T7	4519	0	0	0
T8	1998	0	0	0
T9	45187	0	0	0
T10	134409	38	0	0
T11	186421	51	0	0
T12	3127	0	0	0
T22	1707	0	0	0
T36	0	14	0	0
T38	0	1	0	0
T42	0	6	0	0
T54	0	11	0	0
T94	0	13	0	0
T95	0	7	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	14692	0	0
T1	29255	75	0	0
T2	1452	0	0	0
T3	45091	37	0	0
T4	235646	229	0	0
T5	254002	269	0	0
T6	5294	0	0	0
T7	4519	4	0	0
T8	1998	0	0	0
T9	45187	75	0	0
T10	134409	165	0	0
T11	0	223	0	0
T12	0	8	0	0
T22	0	2	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	1259	0	0
T4	235646	10	0	0
T5	254002	10	0	0
T6	5294	0	0	0
T7	4519	0	0	0
T8	1998	0	0	0
T9	45187	0	0	0
T10	134409	38	0	0
T11	186421	51	0	0
T12	3127	0	0	0
T22	1707	0	0	0
T36	0	14	0	0
T38	0	1	0	0
T42	0	6	0	0
T54	0	11	0	0
T94	0	13	0	0
T95	0	7	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	14721	0	0
T1	29255	75	0	0
T2	1452	0	0	0
T3	45091	37	0	0
T4	235646	230	0	0
T5	254002	269	0	0
T6	5294	0	0	0
T7	4519	4	0	0
T8	1998	0	0	0
T9	45187	75	0	0
T10	134409	163	0	0
T11	0	218	0	0
T12	0	8	0	0
T22	0	2	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	1298	0	0
T4	235646	13	0	0
T5	254002	10	0	0
T6	5294	0	0	0
T7	4519	0	0	0
T8	1998	0	0	0
T9	45187	0	0	0
T10	134409	35	0	0
T11	186421	47	0	0
T12	3127	0	0	0
T22	1707	0	0	0
T36	0	14	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	8	0	0
T54	0	12	0	0
T94	0	14	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	14721	0	0
T1	29255	75	0	0
T2	1452	0	0	0
T3	45091	37	0	0
T4	235646	230	0	0
T5	254002	269	0	0
T6	5294	0	0	0
T7	4519	4	0	0
T8	1998	0	0	0
T9	45187	75	0	0
T10	134409	163	0	0
T11	0	218	0	0
T12	0	8	0	0
T22	0	2	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	1298	0	0
T4	235646	13	0	0
T5	254002	10	0	0
T6	5294	0	0	0
T7	4519	0	0	0
T8	1998	0	0	0
T9	45187	0	0	0
T10	134409	35	0	0
T11	186421	47	0	0
T12	3127	0	0	0
T22	1707	0	0	0
T36	0	14	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	8	0	0
T54	0	12	0	0
T94	0	14	0	0