Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12938327	7994	0	0
alert_regwen_rd_A	12938327	3931	0	0
cpu_regwen_rd_A	12938327	3968	0	0
sw_rst_ctrl_n_0_rd_A	12938327	8695	0	0
sw_rst_ctrl_n_1_rd_A	12938327	9143	0	0
sw_rst_ctrl_n_2_rd_A	12938327	8834	0	0
sw_rst_ctrl_n_3_rd_A	12938327	8779	0	0
sw_rst_ctrl_n_4_rd_A	12938327	8742	0	0
sw_rst_ctrl_n_5_rd_A	12938327	8809	0	0
sw_rst_ctrl_n_6_rd_A	12938327	8791	0	0
sw_rst_ctrl_n_7_rd_A	12938327	8782	0	0
sw_rst_regwen_0_rd_A	12938327	4262	0	0
sw_rst_regwen_1_rd_A	12938327	4361	0	0
sw_rst_regwen_2_rd_A	12938327	4340	0	0
sw_rst_regwen_3_rd_A	12938327	4280	0	0
sw_rst_regwen_4_rd_A	12938327	4401	0	0
sw_rst_regwen_5_rd_A	12938327	4393	0	0
sw_rst_regwen_6_rd_A	12938327	4456	0	0
sw_rst_regwen_7_rd_A	12938327	4463	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	7994	0	0
T56	3430	12	0	0
T57	27978	2	0	0
T58	3737	95	0	0
T59	9521	3	0	0
T61	4098	316	0	0
T76	10135	2	0	0
T77	4023	89	0	0
T78	2707	265	0	0
T83	3762	293	0	0
T96	3577	8	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	3931	0	0
T3	39963	82	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T50	0	70	0	0
T67	0	70	0	0
T100	0	231	0	0
T103	0	326	0	0
T115	0	80	0	0
T116	0	160	0	0
T117	0	406	0	0
T118	0	47	0	0
T119	0	41	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	3968	0	0
T3	39963	68	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T50	0	79	0	0
T67	0	65	0	0
T100	0	173	0	0
T103	0	418	0	0
T115	0	76	0	0
T116	0	186	0	0
T117	0	448	0	0
T118	0	23	0	0
T119	0	69	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	8695	0	0
T3	39963	71	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	212	0	0
T50	0	66	0	0
T100	0	425	0	0
T115	0	135	0	0
T120	0	155	0	0
T121	0	121	0	0
T122	0	144	0	0
T123	0	110	0	0
T124	0	9	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	9143	0	0
T3	39963	47	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	219	0	0
T50	0	77	0	0
T100	0	404	0	0
T115	0	156	0	0
T120	0	106	0	0
T121	0	176	0	0
T122	0	101	0	0
T123	0	177	0	0
T124	0	14	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	8834	0	0
T3	39963	71	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	184	0	0
T50	0	61	0	0
T100	0	328	0	0
T115	0	138	0	0
T120	0	154	0	0
T121	0	133	0	0
T122	0	90	0	0
T123	0	110	0	0
T124	0	28	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	8779	0	0
T3	39963	67	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	242	0	0
T50	0	60	0	0
T100	0	377	0	0
T115	0	166	0	0
T120	0	140	0	0
T121	0	152	0	0
T122	0	126	0	0
T123	0	176	0	0
T124	0	19	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	8742	0	0
T3	39963	83	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	221	0	0
T50	0	52	0	0
T100	0	345	0	0
T115	0	145	0	0
T120	0	138	0	0
T121	0	132	0	0
T122	0	108	0	0
T123	0	131	0	0
T124	0	12	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	8809	0	0
T3	39963	49	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	193	0	0
T50	0	77	0	0
T100	0	413	0	0
T115	0	143	0	0
T120	0	144	0	0
T121	0	138	0	0
T122	0	116	0	0
T123	0	131	0	0
T124	0	26	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	8791	0	0
T3	39963	62	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	171	0	0
T50	0	82	0	0
T100	0	413	0	0
T115	0	189	0	0
T120	0	137	0	0
T121	0	169	0	0
T122	0	125	0	0
T123	0	158	0	0
T124	0	29	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	8782	0	0
T3	39963	63	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	219	0	0
T50	0	61	0	0
T100	0	308	0	0
T115	0	131	0	0
T120	0	122	0	0
T121	0	87	0	0
T122	0	111	0	0
T123	0	200	0	0
T124	0	20	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	4262	0	0
T3	39963	67	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	32	0	0
T50	0	55	0	0
T100	0	195	0	0
T115	0	79	0	0
T120	0	45	0	0
T121	0	16	0	0
T122	0	17	0	0
T123	0	20	0	0
T125	0	13	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	4361	0	0
T3	39963	69	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	34	0	0
T50	0	52	0	0
T100	0	184	0	0
T115	0	74	0	0
T120	0	25	0	0
T121	0	12	0	0
T122	0	24	0	0
T123	0	9	0	0
T125	0	9	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	4340	0	0
T3	39963	52	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	36	0	0
T50	0	77	0	0
T100	0	233	0	0
T103	0	339	0	0
T115	0	70	0	0
T120	0	27	0	0
T121	0	29	0	0
T122	0	9	0	0
T123	0	12	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	4280	0	0
T3	39963	55	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	36	0	0
T50	0	62	0	0
T100	0	195	0	0
T115	0	52	0	0
T120	0	25	0	0
T121	0	30	0	0
T122	0	8	0	0
T123	0	11	0	0
T125	0	4	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	4401	0	0
T3	39963	77	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	30	0	0
T50	0	51	0	0
T100	0	214	0	0
T115	0	80	0	0
T120	0	42	0	0
T121	0	27	0	0
T122	0	5	0	0
T123	0	36	0	0
T125	0	7	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	4393	0	0
T3	39963	68	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	30	0	0
T50	0	56	0	0
T100	0	196	0	0
T115	0	66	0	0
T120	0	18	0	0
T121	0	17	0	0
T122	0	19	0	0
T123	0	15	0	0
T125	0	10	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	4456	0	0
T3	39963	73	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	39	0	0
T50	0	77	0	0
T100	0	184	0	0
T115	0	72	0	0
T120	0	31	0	0
T121	0	16	0	0
T122	0	4	0	0
T123	0	14	0	0
T125	0	7	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12938327	4463	0	0
T3	39963	73	0	0
T4	204920	0	0	0
T5	221065	0	0	0
T6	5107	0	0	0
T7	4422	0	0	0
T8	1932	0	0	0
T9	42136	0	0	0
T10	119259	0	0	0
T11	165244	0	0	0
T12	2475	0	0	0
T36	0	36	0	0
T50	0	92	0	0
T100	0	198	0	0
T115	0	95	0	0
T120	0	43	0	0
T121	0	19	0	0
T122	0	23	0	0
T123	0	27	0	0
T125	0	7	0	0