Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	57263543	9709	0	0
CascadeEffAonToRstPorAboveRise_A	57263543	9709	0	0
CascadeEffAonToRstPorIoAboveFall_A	54971793	9709	0	0
CascadeEffAonToRstPorIoAboveRise_A	54971793	9709	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27486797	9709	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27486797	9709	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13743217	9709	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13743217	9709	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27486607	9709	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27486607	9709	0	0
CascadeLcToLcAboveFall_A	57263543	23178	0	0
CascadeLcToLcAboveRise_A	57263543	23178	0	0
CascadeLcToLcAonAboveFall_A	1735563	23178	0	0
CascadeLcToLcAonAboveRise_A	1735563	23178	0	0
CascadeLcToLcShadowedAboveFall_A	57263543	23178	0	0
CascadeLcToLcShadowedAboveRise_A	57263543	23178	0	0
CascadePorToAonAboveFall_A	1735563	7780	0	0
CascadeSysToSysAboveFall_A	57263543	23178	0	0
CascadeSysToSysAboveRise_A	57263543	23178	0	0
ScanRstToAonRise_A	1735563	250	0	0
StablePorToAonRise_A	1735563	9709	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12161133	23178	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12161133	23178	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12161133	23178	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12161133	23178	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13743217	23178	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13743217	23178	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12161133	23178	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12161133	23178	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12161133	23178	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12161133	23178	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57263543	9709	0	0
T1	121906	27	0	0
T2	6058	1	0	0
T3	187890	20	0	0
T4	981796	134	0	0
T5	105828	137	0	0
T6	22061	2	0	0
T7	18832	2	0	0
T8	8331	1	0	0
T9	188262	27	0	0
T10	560059	60	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57263543	9709	0	0
T1	121906	27	0	0
T2	6058	1	0	0
T3	187890	20	0	0
T4	981796	134	0	0
T5	105828	137	0	0
T6	22061	2	0	0
T7	18832	2	0	0
T8	8331	1	0	0
T9	188262	27	0	0
T10	560059	60	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54971793	9709	0	0
T1	117030	27	0	0
T2	5816	1	0	0
T3	180368	20	0	0
T4	942462	134	0	0
T5	101586	137	0	0
T6	21177	2	0	0
T7	18085	2	0	0
T8	7997	1	0	0
T9	180736	27	0	0
T10	537599	60	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54971793	9709	0	0
T1	117030	27	0	0
T2	5816	1	0	0
T3	180368	20	0	0
T4	942462	134	0	0
T5	101586	137	0	0
T6	21177	2	0	0
T7	18085	2	0	0
T8	7997	1	0	0
T9	180736	27	0	0
T10	537599	60	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27486797	9709	0	0
T1	58512	27	0	0
T2	2907	1	0	0
T3	90185	20	0	0
T4	471278	134	0	0
T5	507996	137	0	0
T6	10589	2	0	0
T7	9042	2	0	0
T8	3998	1	0	0
T9	90377	27	0	0
T10	268822	60	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27486797	9709	0	0
T1	58512	27	0	0
T2	2907	1	0	0
T3	90185	20	0	0
T4	471278	134	0	0
T5	507996	137	0	0
T6	10589	2	0	0
T7	9042	2	0	0
T8	3998	1	0	0
T9	90377	27	0	0
T10	268822	60	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	9709	0	0
T1	29255	27	0	0
T2	1452	1	0	0
T3	45091	20	0	0
T4	235646	134	0	0
T5	254002	137	0	0
T6	5294	2	0	0
T7	4519	2	0	0
T8	1998	1	0	0
T9	45187	27	0	0
T10	134409	60	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	9709	0	0
T1	29255	27	0	0
T2	1452	1	0	0
T3	45091	20	0	0
T4	235646	134	0	0
T5	254002	137	0	0
T6	5294	2	0	0
T7	4519	2	0	0
T8	1998	1	0	0
T9	45187	27	0	0
T10	134409	60	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27486607	9709	0	0
T1	58496	27	0	0
T2	2908	1	0	0
T3	90192	20	0	0
T4	471260	134	0	0
T5	507986	137	0	0
T6	10589	2	0	0
T7	9042	2	0	0
T8	3998	1	0	0
T9	90361	27	0	0
T10	268820	60	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27486607	9709	0	0
T1	58496	27	0	0
T2	2908	1	0	0
T3	90192	20	0	0
T4	471260	134	0	0
T5	507986	137	0	0
T6	10589	2	0	0
T7	9042	2	0	0
T8	3998	1	0	0
T9	90361	27	0	0
T10	268820	60	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57263543	23178	0	0
T1	121906	102	0	0
T2	6058	1	0	0
T3	187890	57	0	0
T4	981796	353	0	0
T5	105828	398	0	0
T6	22061	2	0	0
T7	18832	6	0	0
T8	8331	1	0	0
T9	188262	102	0	0
T10	560059	188	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57263543	23178	0	0
T1	121906	102	0	0
T2	6058	1	0	0
T3	187890	57	0	0
T4	981796	353	0	0
T5	105828	398	0	0
T6	22061	2	0	0
T7	18832	6	0	0
T8	8331	1	0	0
T9	188262	102	0	0
T10	560059	188	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1735563	23178	0	0
T1	3670	102	0	0
T2	180	1	0	0
T3	5715	57	0	0
T4	29971	353	0	0
T5	32300	398	0	0
T6	659	2	0	0
T7	564	6	0	0
T8	249	1	0	0
T9	5664	102	0	0
T10	17051	188	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1735563	23178	0	0
T1	3670	102	0	0
T2	180	1	0	0
T3	5715	57	0	0
T4	29971	353	0	0
T5	32300	398	0	0
T6	659	2	0	0
T7	564	6	0	0
T8	249	1	0	0
T9	5664	102	0	0
T10	17051	188	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57263543	23178	0	0
T1	121906	102	0	0
T2	6058	1	0	0
T3	187890	57	0	0
T4	981796	353	0	0
T5	105828	398	0	0
T6	22061	2	0	0
T7	18832	6	0	0
T8	8331	1	0	0
T9	188262	102	0	0
T10	560059	188	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57263543	23178	0	0
T1	121906	102	0	0
T2	6058	1	0	0
T3	187890	57	0	0
T4	981796	353	0	0
T5	105828	398	0	0
T6	22061	2	0	0
T7	18832	6	0	0
T8	8331	1	0	0
T9	188262	102	0	0
T10	560059	188	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1735563	7780	0	0
T1	3670	27	0	0
T2	180	1	0	0
T3	5715	8	0	0
T4	29971	67	0	0
T5	32300	63	0	0
T6	659	21	0	0
T7	564	1	0	0
T8	249	1	0	0
T9	5664	27	0	0
T10	17051	28	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57263543	23178	0	0
T1	121906	102	0	0
T2	6058	1	0	0
T3	187890	57	0	0
T4	981796	353	0	0
T5	105828	398	0	0
T6	22061	2	0	0
T7	18832	6	0	0
T8	8331	1	0	0
T9	188262	102	0	0
T10	560059	188	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57263543	23178	0	0
T1	121906	102	0	0
T2	6058	1	0	0
T3	187890	57	0	0
T4	981796	353	0	0
T5	105828	398	0	0
T6	22061	2	0	0
T7	18832	6	0	0
T8	8331	1	0	0
T9	188262	102	0	0
T10	560059	188	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1735563	250	0	0
T3	5715	4	0	0
T4	29971	7	0	0
T5	32300	7	0	0
T6	659	0	0	0
T7	564	0	0	0
T8	249	0	0	0
T9	5664	0	0	0
T10	17051	3	0	0
T11	23621	3	0	0
T12	390	0	0	0
T42	0	6	0	0
T45	0	3	0	0
T95	0	2	0	0
T98	0	6	0	0
T106	0	3	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1735563	9709	0	0
T1	3670	27	0	0
T2	180	1	0	0
T3	5715	20	0	0
T4	29971	134	0	0
T5	32300	137	0	0
T6	659	2	0	0
T7	564	2	0	0
T8	249	1	0	0
T9	5664	27	0	0
T10	17051	60	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12161133	23178	0	0
T1	26185	102	0	0
T2	1411	1	0	0
T3	39963	57	0	0
T4	204920	353	0	0
T5	221065	398	0	0
T6	5107	2	0	0
T7	4422	6	0	0
T8	1932	1	0	0
T9	42136	102	0	0
T10	119259	188	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12161133	23178	0	0
T1	26185	102	0	0
T2	1411	1	0	0
T3	39963	57	0	0
T4	204920	353	0	0
T5	221065	398	0	0
T6	5107	2	0	0
T7	4422	6	0	0
T8	1932	1	0	0
T9	42136	102	0	0
T10	119259	188	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12161133	23178	0	0
T1	26185	102	0	0
T2	1411	1	0	0
T3	39963	57	0	0
T4	204920	353	0	0
T5	221065	398	0	0
T6	5107	2	0	0
T7	4422	6	0	0
T8	1932	1	0	0
T9	42136	102	0	0
T10	119259	188	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12161133	23178	0	0
T1	26185	102	0	0
T2	1411	1	0	0
T3	39963	57	0	0
T4	204920	353	0	0
T5	221065	398	0	0
T6	5107	2	0	0
T7	4422	6	0	0
T8	1932	1	0	0
T9	42136	102	0	0
T10	119259	188	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	23178	0	0
T1	29255	102	0	0
T2	1452	1	0	0
T3	45091	57	0	0
T4	235646	353	0	0
T5	254002	398	0	0
T6	5294	2	0	0
T7	4519	6	0	0
T8	1998	1	0	0
T9	45187	102	0	0
T10	134409	188	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13743217	23178	0	0
T1	29255	102	0	0
T2	1452	1	0	0
T3	45091	57	0	0
T4	235646	353	0	0
T5	254002	398	0	0
T6	5294	2	0	0
T7	4519	6	0	0
T8	1998	1	0	0
T9	45187	102	0	0
T10	134409	188	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12161133	23178	0	0
T1	26185	102	0	0
T2	1411	1	0	0
T3	39963	57	0	0
T4	204920	353	0	0
T5	221065	398	0	0
T6	5107	2	0	0
T7	4422	6	0	0
T8	1932	1	0	0
T9	42136	102	0	0
T10	119259	188	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12161133	23178	0	0
T1	26185	102	0	0
T2	1411	1	0	0
T3	39963	57	0	0
T4	204920	353	0	0
T5	221065	398	0	0
T6	5107	2	0	0
T7	4422	6	0	0
T8	1932	1	0	0
T9	42136	102	0	0
T10	119259	188	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12161133	23178	0	0
T1	26185	102	0	0
T2	1411	1	0	0
T3	39963	57	0	0
T4	204920	353	0	0
T5	221065	398	0	0
T6	5107	2	0	0
T7	4422	6	0	0
T8	1932	1	0	0
T9	42136	102	0	0
T10	119259	188	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12161133	23178	0	0
T1	26185	102	0	0
T2	1411	1	0	0
T3	39963	57	0	0
T4	204920	353	0	0
T5	221065	398	0	0
T6	5107	2	0	0
T7	4422	6	0	0
T8	1932	1	0	0
T9	42136	102	0	0
T10	119259	188	0	0