Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	601431	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

362103

1

T1

129

T2

2373

T3

128

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	513012	1			T1	176		T2	3511		T3	186
values[0x0]	224617	1			T1	83		T2	1560		T3	106
values[0x1]	225905	1			T1	97		T2	1505		T3	87

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	504888	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

458646

1

T1

175

T2

3003

T3

154

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3715	1			T2	29		T3	2		T5	79
valid_sources[0x01]	3806	1			T2	24		T3	1		T5	69
valid_sources[0x02]	4340	1			T2	33		T3	5		T5	42
valid_sources[0x03]	2989	1			T2	26		T5	21		T8	7
valid_sources[0x04]	3665	1			T1	3		T2	24		T5	30
valid_sources[0x05]	2830	1			T2	24		T3	2		T5	25
valid_sources[0x06]	3754	1			T2	17		T3	1		T5	52
valid_sources[0x07]	7447	1			T2	21		T3	1		T5	95
valid_sources[0x08]	3997	1			T2	27		T5	65		T7	2
valid_sources[0x09]	3946	1			T2	24		T4	1		T5	69
valid_sources[0x0a]	3071	1			T1	4		T2	22		T3	8
valid_sources[0x0b]	3116	1			T2	28		T5	114		T8	11
valid_sources[0x0c]	2737	1			T2	22		T5	27		T8	16
valid_sources[0x0d]	3455	1			T2	31		T5	98		T8	17
valid_sources[0x0e]	3417	1			T2	15		T3	6		T5	53
valid_sources[0x0f]	3277	1			T2	17		T5	63		T7	1
valid_sources[0x10]	6215	1			T2	25		T3	3		T5	148
valid_sources[0x11]	6868	1			T2	26		T3	3		T5	108
valid_sources[0x12]	3079	1			T2	13		T5	79		T8	9
valid_sources[0x13]	3730	1			T2	27		T3	4		T5	27
valid_sources[0x14]	3966	1			T2	26		T3	1		T5	116
valid_sources[0x15]	3136	1			T1	3		T2	29		T3	1
valid_sources[0x16]	5201	1			T1	4		T2	30		T5	79
valid_sources[0x17]	3240	1			T2	25		T3	3		T5	66
valid_sources[0x18]	3349	1			T2	24		T3	4		T5	53
valid_sources[0x19]	4151	1			T2	24		T3	1		T5	28
valid_sources[0x1a]	3697	1			T2	25		T5	58		T7	2
valid_sources[0x1b]	4241	1			T2	27		T3	3		T5	66
valid_sources[0x1c]	3603	1			T2	30		T3	1		T5	111
valid_sources[0x1d]	5685	1			T2	33		T3	6		T5	45
valid_sources[0x1e]	6210	1			T2	22		T5	116		T6	3200
valid_sources[0x1f]	6610	1			T2	34		T3	1		T5	55
valid_sources[0x20]	5566	1			T1	2		T2	23		T3	2
valid_sources[0x21]	3608	1			T2	16		T3	1		T4	1
valid_sources[0x22]	3128	1			T2	15		T3	2		T5	20
valid_sources[0x23]	4095	1			T2	26		T5	60		T7	2
valid_sources[0x24]	3408	1			T2	19		T3	1		T5	81
valid_sources[0x25]	3722	1			T2	27		T5	117		T8	17
valid_sources[0x26]	3390	1			T1	2		T2	31		T3	1
valid_sources[0x27]	4381	1			T2	28		T3	5		T5	115
valid_sources[0x28]	3305	1			T1	4		T2	29		T3	1
valid_sources[0x29]	3085	1			T2	27		T3	7		T5	77
valid_sources[0x2a]	3831	1			T2	27		T3	4		T5	102
valid_sources[0x2b]	3609	1			T2	36		T5	28		T7	3
valid_sources[0x2c]	4167	1			T2	30		T5	45		T7	1
valid_sources[0x2d]	3493	1			T2	34		T3	1		T5	44
valid_sources[0x2e]	3609	1			T2	32		T3	1		T5	57
valid_sources[0x2f]	6646	1			T1	24		T2	22		T3	1
valid_sources[0x30]	4090	1			T2	17		T3	6		T5	63
valid_sources[0x31]	3462	1			T2	33		T3	1		T5	70
valid_sources[0x32]	4171	1			T2	23		T5	89		T8	7
valid_sources[0x33]	3287	1			T2	29		T3	1		T5	61
valid_sources[0x34]	3933	1			T2	17		T4	1		T5	71
valid_sources[0x35]	3125	1			T2	24		T3	3		T5	48
valid_sources[0x36]	3205	1			T2	25		T3	1		T5	60
valid_sources[0x37]	2778	1			T2	20		T3	1		T5	43
valid_sources[0x38]	3045	1			T2	41		T4	1		T5	31
valid_sources[0x39]	3577	1			T2	16		T3	3		T5	179
valid_sources[0x3a]	3368	1			T2	21		T5	43		T7	1
valid_sources[0x3b]	3770	1			T1	3		T2	32		T3	3
valid_sources[0x3c]	3280	1			T2	30		T3	3		T5	33
valid_sources[0x3d]	3091	1			T2	27		T5	105		T7	1
valid_sources[0x3e]	3441	1			T2	32		T5	81		T7	1
valid_sources[0x3f]	3452	1			T1	20		T2	36		T3	7
valid_sources[0x40]	2890	1			T2	34		T3	4		T5	21
valid_sources[0x41]	4149	1			T2	17		T5	82		T8	9
valid_sources[0x42]	3463	1			T2	21		T5	99		T8	11
valid_sources[0x43]	3088	1			T2	13		T3	1		T5	76
valid_sources[0x44]	3920	1			T2	31		T3	1		T5	63
valid_sources[0x45]	4108	1			T2	22		T3	2		T5	63
valid_sources[0x46]	3453	1			T2	24		T5	34		T7	1
valid_sources[0x47]	3490	1			T2	20		T5	130		T7	2
valid_sources[0x48]	3320	1			T1	1		T2	17		T3	1
valid_sources[0x49]	2962	1			T1	15		T2	25		T3	2
valid_sources[0x4a]	3349	1			T2	36		T5	104		T7	1
valid_sources[0x4b]	3938	1			T2	15		T3	1		T5	79
valid_sources[0x4c]	3113	1			T2	22		T5	35		T7	2
valid_sources[0x4d]	3650	1			T2	30		T3	2		T5	76
valid_sources[0x4e]	3256	1			T2	13		T5	54		T8	6
valid_sources[0x4f]	3176	1			T1	3		T2	23		T5	61
valid_sources[0x50]	3221	1			T2	28		T5	48		T8	16
valid_sources[0x51]	3223	1			T2	24		T3	2		T5	39
valid_sources[0x52]	3872	1			T2	23		T3	1		T5	51
valid_sources[0x53]	5139	1			T2	31		T3	2		T5	18
valid_sources[0x54]	4432	1			T2	24		T3	4		T5	38
valid_sources[0x55]	3615	1			T1	22		T2	31		T3	4
valid_sources[0x56]	3081	1			T2	28		T3	2		T5	35
valid_sources[0x57]	3180	1			T2	23		T3	5		T5	69
valid_sources[0x58]	3548	1			T2	35		T3	3		T5	78
valid_sources[0x59]	3853	1			T2	32		T5	75		T7	1
valid_sources[0x5a]	3752	1			T2	23		T3	2		T5	109
valid_sources[0x5b]	3608	1			T2	36		T5	42		T8	12
valid_sources[0x5c]	4111	1			T2	39		T3	2		T5	54
valid_sources[0x5d]	3785	1			T2	15		T3	1		T5	51
valid_sources[0x5e]	3674	1			T2	28		T3	1		T5	105
valid_sources[0x5f]	3156	1			T2	15		T3	2		T5	28
valid_sources[0x60]	3868	1			T2	39		T3	2		T5	101
valid_sources[0x61]	3507	1			T1	6		T2	39		T5	75
valid_sources[0x62]	4179	1			T2	25		T5	65		T7	1
valid_sources[0x63]	3514	1			T2	24		T5	69		T8	12
valid_sources[0x64]	3420	1			T2	24		T5	26		T7	1
valid_sources[0x65]	2962	1			T2	23		T5	75		T8	12
valid_sources[0x66]	3925	1			T2	27		T5	23		T8	17
valid_sources[0x67]	3581	1			T1	41		T2	26		T5	97
valid_sources[0x68]	4025	1			T2	29		T3	1		T5	52
valid_sources[0x69]	3397	1			T2	19		T3	1		T5	37
valid_sources[0x6a]	3651	1			T2	21		T5	103		T8	13
valid_sources[0x6b]	3370	1			T1	22		T2	22		T3	2
valid_sources[0x6c]	3094	1			T2	21		T5	35		T7	2
valid_sources[0x6d]	3538	1			T2	18		T3	1		T5	34
valid_sources[0x6e]	3493	1			T2	30		T5	26		T8	21
valid_sources[0x6f]	4577	1			T2	38		T5	60		T7	1
valid_sources[0x70]	3088	1			T2	17		T3	2		T5	67
valid_sources[0x71]	3318	1			T2	21		T3	2		T4	2
valid_sources[0x72]	4224	1			T2	26		T5	142		T8	15
valid_sources[0x73]	4067	1			T2	22		T3	1		T5	23
valid_sources[0x74]	5445	1			T2	37		T3	2		T5	81
valid_sources[0x75]	3904	1			T1	6		T2	23		T3	1
valid_sources[0x76]	3354	1			T2	25		T3	3		T5	38
valid_sources[0x77]	4764	1			T2	13		T3	1		T5	81
valid_sources[0x78]	3744	1			T2	24		T3	6		T5	29
valid_sources[0x79]	3962	1			T2	14		T3	2		T5	14
valid_sources[0x7a]	4245	1			T2	32		T3	3		T5	75
valid_sources[0x7b]	3237	1			T2	35		T3	2		T5	40
valid_sources[0x7c]	4363	1			T2	33		T5	96		T7	1
valid_sources[0x7d]	4497	1			T2	15		T3	3		T5	141
valid_sources[0x7e]	3149	1			T2	27		T5	53		T7	1
valid_sources[0x7f]	3126	1			T2	31		T3	4		T5	104
valid_sources[0x80]	4713	1			T2	18		T3	2		T5	102

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

241264

1

T1

92

T2

1613

T3

84

values[0x0]

all_enables

biggest_size

78335

1

T1

22

T2

492

T3

25

values[0x1]

all_enables

biggest_size

42504

1

T1

15

T2

268

T3

19