Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12550112	13706	0	0
gen_assertions[0].RstEnOn_A	12550112	1087	0	0
gen_assertions[0].RstNOff_A	12550112	13706	0	0
gen_assertions[0].RstNOn_A	12550112	1087	0	0
gen_assertions[1].RstEnOff_A	50199610	12492	0	0
gen_assertions[1].RstEnOn_A	50199610	1086	0	0
gen_assertions[1].RstNOff_A	50199610	12492	0	0
gen_assertions[1].RstNOn_A	50199610	1086	0	0
gen_assertions[2].RstEnOff_A	25100336	12513	0	0
gen_assertions[2].RstEnOn_A	25100336	1060	0	0
gen_assertions[2].RstNOff_A	25100336	12513	0	0
gen_assertions[2].RstNOn_A	25100336	1060	0	0
gen_assertions[3].RstEnOff_A	25100261	12580	0	0
gen_assertions[3].RstEnOn_A	25100261	1122	0	0
gen_assertions[3].RstNOff_A	25100261	12580	0	0
gen_assertions[3].RstNOn_A	25100261	1122	0	0
gen_assertions[4].RstEnOff_A	1584199	20986	0	0
gen_assertions[4].RstEnOn_A	1584199	1141	0	0
gen_assertions[4].RstNOff_A	1584199	20986	0	0
gen_assertions[4].RstNOn_A	1584199	1141	0	0
gen_assertions[5].RstEnOff_A	12550112	13959	0	0
gen_assertions[5].RstEnOn_A	12550112	1223	0	0
gen_assertions[5].RstNOff_A	12550112	13959	0	0
gen_assertions[5].RstNOn_A	12550112	1223	0	0
gen_assertions[6].RstEnOff_A	12550112	13999	0	0
gen_assertions[6].RstEnOn_A	12550112	1264	0	0
gen_assertions[6].RstNOff_A	12550112	13999	0	0
gen_assertions[6].RstNOn_A	12550112	1264	0	0
gen_assertions[7].RstEnOff_A	12550112	14077	0	0
gen_assertions[7].RstEnOn_A	12550112	1335	0	0
gen_assertions[7].RstNOff_A	12550112	14077	0	0
gen_assertions[7].RstNOn_A	12550112	1335	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	13706	0	0
T1	6436	7	0	0
T2	82927	101	0	0
T3	4892	5	0	0
T4	1881	0	0	0
T5	269439	232	0	0
T6	29575	75	0	0
T7	2432	4	0	0
T8	56394	75	0	0
T9	3288	15	0	0
T10	5261	17	0	0
T12	0	75	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	1087	0	0
T1	6436	7	0	0
T2	82927	9	0	0
T3	4892	1	0	0
T4	1881	0	0	0
T5	269439	14	0	0
T6	29575	0	0	0
T7	2432	0	0	0
T8	56394	0	0	0
T9	3288	4	0	0
T10	5261	2	0	0
T22	0	8	0	0
T25	0	6	0	0
T26	0	7	0	0
T41	0	53	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	13706	0	0
T1	6436	7	0	0
T2	82927	101	0	0
T3	4892	5	0	0
T4	1881	0	0	0
T5	269439	232	0	0
T6	29575	75	0	0
T7	2432	4	0	0
T8	56394	75	0	0
T9	3288	15	0	0
T10	5261	17	0	0
T12	0	75	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	1087	0	0
T1	6436	7	0	0
T2	82927	9	0	0
T3	4892	1	0	0
T4	1881	0	0	0
T5	269439	14	0	0
T6	29575	0	0	0
T7	2432	0	0	0
T8	56394	0	0	0
T9	3288	4	0	0
T10	5261	2	0	0
T22	0	8	0	0
T25	0	6	0	0
T26	0	7	0	0
T41	0	53	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50199610	12492	0	0
T1	25752	3	0	0
T2	331712	91	0	0
T3	19567	4	0	0
T4	7532	0	0	0
T5	107771	210	0	0
T6	118301	70	0	0
T7	9733	4	0	0
T8	225555	65	0	0
T9	13160	11	0	0
T10	21053	15	0	0
T12	0	66	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50199610	1086	0	0
T1	25752	3	0	0
T2	331712	8	0	0
T3	19567	0	0	0
T4	7532	0	0	0
T5	107771	19	0	0
T6	118301	0	0	0
T7	9733	0	0	0
T8	225555	0	0	0
T9	13160	7	0	0
T10	21053	1	0	0
T22	0	9	0	0
T25	0	5	0	0
T26	0	9	0	0
T41	0	56	0	0
T72	0	25	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50199610	12492	0	0
T1	25752	3	0	0
T2	331712	91	0	0
T3	19567	4	0	0
T4	7532	0	0	0
T5	107771	210	0	0
T6	118301	70	0	0
T7	9733	4	0	0
T8	225555	65	0	0
T9	13160	11	0	0
T10	21053	15	0	0
T12	0	66	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50199610	1086	0	0
T1	25752	3	0	0
T2	331712	8	0	0
T3	19567	0	0	0
T4	7532	0	0	0
T5	107771	19	0	0
T6	118301	0	0	0
T7	9733	0	0	0
T8	225555	0	0	0
T9	13160	7	0	0
T10	21053	1	0	0
T22	0	9	0	0
T25	0	5	0	0
T26	0	9	0	0
T41	0	56	0	0
T72	0	25	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25100336	12513	0	0
T1	12874	5	0	0
T2	165872	92	0	0
T3	9784	4	0	0
T4	3765	0	0	0
T5	538859	209	0	0
T6	59151	70	0	0
T7	4863	4	0	0
T8	112785	65	0	0
T9	6580	11	0	0
T10	10526	15	0	0
T12	0	66	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25100336	1060	0	0
T1	12874	5	0	0
T2	165872	9	0	0
T3	9784	0	0	0
T4	3765	0	0	0
T5	538859	16	0	0
T6	59151	0	0	0
T7	4863	0	0	0
T8	112785	0	0	0
T9	6580	0	0	0
T10	10526	0	0	0
T22	0	10	0	0
T25	0	8	0	0
T26	0	9	0	0
T41	0	55	0	0
T72	0	20	0	0
T73	0	6	0	0
T74	0	6	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25100336	12513	0	0
T1	12874	5	0	0
T2	165872	92	0	0
T3	9784	4	0	0
T4	3765	0	0	0
T5	538859	209	0	0
T6	59151	70	0	0
T7	4863	4	0	0
T8	112785	65	0	0
T9	6580	11	0	0
T10	10526	15	0	0
T12	0	66	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25100336	1060	0	0
T1	12874	5	0	0
T2	165872	9	0	0
T3	9784	0	0	0
T4	3765	0	0	0
T5	538859	16	0	0
T6	59151	0	0	0
T7	4863	0	0	0
T8	112785	0	0	0
T9	6580	0	0	0
T10	10526	0	0	0
T22	0	10	0	0
T25	0	8	0	0
T26	0	9	0	0
T41	0	55	0	0
T72	0	20	0	0
T73	0	6	0	0
T74	0	6	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25100261	12580	0	0
T1	12874	5	0	0
T2	165850	93	0	0
T3	9785	4	0	0
T4	3765	0	0	0
T5	538858	208	0	0
T6	59138	70	0	0
T7	4863	4	0	0
T8	112789	65	0	0
T9	6579	11	0	0
T10	10527	15	0	0
T12	0	66	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25100261	1122	0	0
T1	12874	5	0	0
T2	165850	10	0	0
T3	9785	0	0	0
T4	3765	0	0	0
T5	538858	17	0	0
T6	59138	0	0	0
T7	4863	0	0	0
T8	112789	0	0	0
T9	6579	0	0	0
T10	10527	0	0	0
T22	0	11	0	0
T25	0	8	0	0
T26	0	10	0	0
T41	0	63	0	0
T72	0	23	0	0
T73	0	8	0	0
T74	0	6	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25100261	12580	0	0
T1	12874	5	0	0
T2	165850	93	0	0
T3	9785	4	0	0
T4	3765	0	0	0
T5	538858	208	0	0
T6	59138	70	0	0
T7	4863	4	0	0
T8	112789	65	0	0
T9	6579	11	0	0
T10	10527	15	0	0
T12	0	66	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25100261	1122	0	0
T1	12874	5	0	0
T2	165850	10	0	0
T3	9785	0	0	0
T4	3765	0	0	0
T5	538858	17	0	0
T6	59138	0	0	0
T7	4863	0	0	0
T8	112789	0	0	0
T9	6579	0	0	0
T10	10527	0	0	0
T22	0	11	0	0
T25	0	8	0	0
T26	0	10	0	0
T41	0	63	0	0
T72	0	23	0	0
T73	0	8	0	0
T74	0	6	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584199	20986	0	0
T1	804	7	0	0
T2	10488	132	0	0
T3	611	6	0	0
T4	235	1	0	0
T5	33978	341	0	0
T6	3712	75	0	0
T7	302	5	0	0
T8	7064	100	0	0
T9	410	16	0	0
T10	656	18	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584199	1141	0	0
T1	804	5	0	0
T2	10488	4	0	0
T3	611	0	0	0
T4	235	0	0	0
T5	33978	19	0	0
T6	3712	0	0	0
T7	302	0	0	0
T8	7064	0	0	0
T9	410	0	0	0
T10	656	0	0	0
T22	0	12	0	0
T25	0	8	0	0
T26	0	11	0	0
T41	0	57	0	0
T72	0	19	0	0
T73	0	9	0	0
T74	0	8	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584199	20986	0	0
T1	804	7	0	0
T2	10488	132	0	0
T3	611	6	0	0
T4	235	1	0	0
T5	33978	341	0	0
T6	3712	75	0	0
T7	302	5	0	0
T8	7064	100	0	0
T9	410	16	0	0
T10	656	18	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584199	1141	0	0
T1	804	5	0	0
T2	10488	4	0	0
T3	611	0	0	0
T4	235	0	0	0
T5	33978	19	0	0
T6	3712	0	0	0
T7	302	0	0	0
T8	7064	0	0	0
T9	410	0	0	0
T10	656	0	0	0
T22	0	12	0	0
T25	0	8	0	0
T26	0	11	0	0
T41	0	57	0	0
T72	0	19	0	0
T73	0	9	0	0
T74	0	8	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	13959	0	0
T1	6436	5	0	0
T2	82927	102	0	0
T3	4892	4	0	0
T4	1881	0	0	0
T5	269439	232	0	0
T6	29575	75	0	0
T7	2432	4	0	0
T8	56394	75	0	0
T9	3288	15	0	0
T10	5261	17	0	0
T12	0	75	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	1223	0	0
T1	6436	6	0	0
T2	82927	10	0	0
T3	4892	0	0	0
T4	1881	0	0	0
T5	269439	14	0	0
T6	29575	0	0	0
T7	2432	0	0	0
T8	56394	0	0	0
T9	3288	0	0	0
T10	5261	0	0	0
T22	0	15	0	0
T25	0	11	0	0
T26	0	11	0	0
T41	0	55	0	0
T72	0	21	0	0
T73	0	12	0	0
T74	0	8	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	13959	0	0
T1	6436	5	0	0
T2	82927	102	0	0
T3	4892	4	0	0
T4	1881	0	0	0
T5	269439	232	0	0
T6	29575	75	0	0
T7	2432	4	0	0
T8	56394	75	0	0
T9	3288	15	0	0
T10	5261	17	0	0
T12	0	75	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	1223	0	0
T1	6436	6	0	0
T2	82927	10	0	0
T3	4892	0	0	0
T4	1881	0	0	0
T5	269439	14	0	0
T6	29575	0	0	0
T7	2432	0	0	0
T8	56394	0	0	0
T9	3288	0	0	0
T10	5261	0	0	0
T22	0	15	0	0
T25	0	11	0	0
T26	0	11	0	0
T41	0	55	0	0
T72	0	21	0	0
T73	0	12	0	0
T74	0	8	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	13999	0	0
T1	6436	3	0	0
T2	82927	101	0	0
T3	4892	4	0	0
T4	1881	0	0	0
T5	269439	236	0	0
T6	29575	75	0	0
T7	2432	4	0	0
T8	56394	75	0	0
T9	3288	15	0	0
T10	5261	17	0	0
T12	0	75	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	1264	0	0
T1	6436	3	0	0
T2	82927	9	0	0
T3	4892	0	0	0
T4	1881	0	0	0
T5	269439	20	0	0
T6	29575	0	0	0
T7	2432	0	0	0
T8	56394	0	0	0
T9	3288	0	0	0
T10	5261	0	0	0
T22	0	12	0	0
T25	0	10	0	0
T26	0	11	0	0
T41	0	56	0	0
T72	0	21	0	0
T73	0	11	0	0
T74	0	9	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	13999	0	0
T1	6436	3	0	0
T2	82927	101	0	0
T3	4892	4	0	0
T4	1881	0	0	0
T5	269439	236	0	0
T6	29575	75	0	0
T7	2432	4	0	0
T8	56394	75	0	0
T9	3288	15	0	0
T10	5261	17	0	0
T12	0	75	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	1264	0	0
T1	6436	3	0	0
T2	82927	9	0	0
T3	4892	0	0	0
T4	1881	0	0	0
T5	269439	20	0	0
T6	29575	0	0	0
T7	2432	0	0	0
T8	56394	0	0	0
T9	3288	0	0	0
T10	5261	0	0	0
T22	0	12	0	0
T25	0	10	0	0
T26	0	11	0	0
T41	0	56	0	0
T72	0	21	0	0
T73	0	11	0	0
T74	0	9	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	14077	0	0
T1	6436	5	0	0
T2	82927	99	0	0
T3	4892	4	0	0
T4	1881	0	0	0
T5	269439	233	0	0
T6	29575	75	0	0
T7	2432	4	0	0
T8	56394	75	0	0
T9	3288	15	0	0
T10	5261	17	0	0
T12	0	75	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	1335	0	0
T1	6436	6	0	0
T2	82927	7	0	0
T3	4892	0	0	0
T4	1881	0	0	0
T5	269439	14	0	0
T6	29575	0	0	0
T7	2432	0	0	0
T8	56394	0	0	0
T9	3288	0	0	0
T10	5261	0	0	0
T22	0	14	0	0
T25	0	12	0	0
T26	0	15	0	0
T41	0	55	0	0
T72	0	19	0	0
T73	0	13	0	0
T74	0	10	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	14077	0	0
T1	6436	5	0	0
T2	82927	99	0	0
T3	4892	4	0	0
T4	1881	0	0	0
T5	269439	233	0	0
T6	29575	75	0	0
T7	2432	4	0	0
T8	56394	75	0	0
T9	3288	15	0	0
T10	5261	17	0	0
T12	0	75	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	1335	0	0
T1	6436	6	0	0
T2	82927	7	0	0
T3	4892	0	0	0
T4	1881	0	0	0
T5	269439	14	0	0
T6	29575	0	0	0
T7	2432	0	0	0
T8	56394	0	0	0
T9	3288	0	0	0
T10	5261	0	0	0
T22	0	14	0	0
T25	0	12	0	0
T26	0	15	0	0
T41	0	55	0	0
T72	0	19	0	0
T73	0	13	0	0
T74	0	10	0	0