Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11892878	9093	0	0
alert_regwen_rd_A	11892878	4662	0	0
cpu_regwen_rd_A	11892878	4707	0	0
sw_rst_ctrl_n_0_rd_A	11892878	8064	0	0
sw_rst_ctrl_n_1_rd_A	11892878	8328	0	0
sw_rst_ctrl_n_2_rd_A	11892878	7798	0	0
sw_rst_ctrl_n_3_rd_A	11892878	8173	0	0
sw_rst_ctrl_n_4_rd_A	11892878	8510	0	0
sw_rst_ctrl_n_5_rd_A	11892878	8703	0	0
sw_rst_ctrl_n_6_rd_A	11892878	8360	0	0
sw_rst_ctrl_n_7_rd_A	11892878	8096	0	0
sw_rst_regwen_0_rd_A	11892878	4779	0	0
sw_rst_regwen_1_rd_A	11892878	5194	0	0
sw_rst_regwen_2_rd_A	11892878	5168	0	0
sw_rst_regwen_3_rd_A	11892878	5086	0	0
sw_rst_regwen_4_rd_A	11892878	5251	0	0
sw_rst_regwen_5_rd_A	11892878	4944	0	0
sw_rst_regwen_6_rd_A	11892878	5234	0	0
sw_rst_regwen_7_rd_A	11892878	5165	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	9093	0	0
T51	9048	464	0	0
T52	2874	5	0	0
T53	12113	781	0	0
T59	3801	75	0	0
T76	3688	127	0	0
T77	2481	34	0	0
T78	6182	294	0	0
T82	10661	1	0	0
T83	22362	2	0	0
T84	11707	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	4662	0	0
T5	241875	330	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T24	0	69	0	0
T65	0	100	0	0
T72	0	93	0	0
T86	0	74	0	0
T109	0	36	0	0
T110	0	50	0	0
T111	0	653	0	0
T112	0	100	0	0
T113	0	90	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	4707	0	0
T5	241875	339	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T24	0	59	0	0
T65	0	65	0	0
T72	0	87	0	0
T86	0	107	0	0
T109	0	29	0	0
T110	0	60	0	0
T111	0	691	0	0
T112	0	95	0	0
T113	0	64	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	8064	0	0
T5	241875	510	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	197	0	0
T24	0	49	0	0
T72	0	231	0	0
T86	0	71	0	0
T114	0	198	0	0
T115	0	130	0	0
T116	0	26	0	0
T117	0	6	0	0
T118	0	14	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	8328	0	0
T5	241875	505	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	243	0	0
T24	0	62	0	0
T72	0	280	0	0
T86	0	90	0	0
T114	0	189	0	0
T115	0	176	0	0
T116	0	19	0	0
T117	0	13	0	0
T118	0	14	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	7798	0	0
T5	241875	570	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	232	0	0
T24	0	53	0	0
T72	0	273	0	0
T86	0	63	0	0
T114	0	167	0	0
T115	0	140	0	0
T116	0	13	0	0
T117	0	16	0	0
T118	0	18	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	8173	0	0
T5	241875	564	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	203	0	0
T24	0	36	0	0
T72	0	198	0	0
T86	0	61	0	0
T114	0	186	0	0
T115	0	130	0	0
T116	0	5	0	0
T117	0	14	0	0
T118	0	27	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	8510	0	0
T5	241875	530	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	202	0	0
T24	0	52	0	0
T72	0	279	0	0
T86	0	70	0	0
T114	0	209	0	0
T115	0	148	0	0
T116	0	15	0	0
T117	0	6	0	0
T118	0	16	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	8703	0	0
T5	241875	623	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	225	0	0
T24	0	41	0	0
T72	0	242	0	0
T86	0	79	0	0
T114	0	186	0	0
T115	0	160	0	0
T116	0	22	0	0
T117	0	6	0	0
T118	0	16	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	8360	0	0
T5	241875	573	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	254	0	0
T24	0	71	0	0
T72	0	252	0	0
T86	0	85	0	0
T114	0	187	0	0
T115	0	135	0	0
T116	0	16	0	0
T117	0	12	0	0
T118	0	21	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	8096	0	0
T5	241875	520	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	204	0	0
T24	0	53	0	0
T72	0	246	0	0
T86	0	95	0	0
T114	0	182	0	0
T115	0	160	0	0
T116	0	16	0	0
T117	0	3	0	0
T118	0	17	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	4779	0	0
T5	241875	292	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	16	0	0
T24	0	57	0	0
T72	0	67	0	0
T86	0	73	0	0
T114	0	31	0	0
T115	0	20	0	0
T116	0	13	0	0
T117	0	15	0	0
T118	0	7	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	5194	0	0
T5	241875	309	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	37	0	0
T24	0	62	0	0
T72	0	78	0	0
T86	0	75	0	0
T114	0	29	0	0
T115	0	21	0	0
T116	0	6	0	0
T117	0	10	0	0
T118	0	11	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	5168	0	0
T5	241875	346	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	33	0	0
T24	0	64	0	0
T72	0	68	0	0
T86	0	65	0	0
T114	0	29	0	0
T115	0	29	0	0
T116	0	5	0	0
T117	0	12	0	0
T118	0	8	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	5086	0	0
T5	241875	346	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	39	0	0
T24	0	28	0	0
T72	0	86	0	0
T86	0	103	0	0
T114	0	41	0	0
T115	0	25	0	0
T116	0	4	0	0
T117	0	5	0	0
T118	0	4	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	5251	0	0
T5	241875	332	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	34	0	0
T24	0	53	0	0
T72	0	128	0	0
T86	0	93	0	0
T114	0	33	0	0
T115	0	36	0	0
T116	0	6	0	0
T117	0	5	0	0
T118	0	10	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	4944	0	0
T5	241875	359	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	43	0	0
T24	0	42	0	0
T72	0	70	0	0
T86	0	73	0	0
T114	0	28	0	0
T115	0	39	0	0
T116	0	4	0	0
T117	0	6	0	0
T118	0	11	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	5234	0	0
T5	241875	350	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	33	0	0
T24	0	56	0	0
T72	0	81	0	0
T86	0	69	0	0
T114	0	39	0	0
T115	0	36	0	0
T116	0	3	0	0
T117	0	5	0	0
T118	0	4	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11892878	5165	0	0
T5	241875	374	0	0
T6	26151	0	0	0
T7	2286	0	0	0
T8	53242	0	0	0
T9	2212	0	0	0
T10	4002	0	0	0
T11	3600	0	0	0
T12	42087	0	0	0
T13	4518	0	0	0
T14	2319	0	0	0
T22	0	38	0	0
T24	0	51	0	0
T72	0	48	0	0
T86	0	77	0	0
T114	0	40	0	0
T115	0	29	0	0
T116	0	9	0	0
T117	0	12	0	0
T118	0	3	0	0