Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T5,T7
1	0	Covered	T2,T3,T5

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52292382	8416	0	0
CascadeEffAonToRstPorAboveRise_A	52292382	8416	0	0
CascadeEffAonToRstPorIoAboveFall_A	50199610	8416	0	0
CascadeEffAonToRstPorIoAboveRise_A	50199610	8416	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25100336	8416	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25100336	8416	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12550112	8416	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12550112	8416	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25100261	8416	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25100261	8416	0	0
CascadeLcToLcAboveFall_A	52292382	21198	0	0
CascadeLcToLcAboveRise_A	52292382	21198	0	0
CascadeLcToLcAonAboveFall_A	1584199	21198	0	0
CascadeLcToLcAonAboveRise_A	1584199	21198	0	0
CascadeLcToLcShadowedAboveFall_A	52292382	21198	0	0
CascadeLcToLcShadowedAboveRise_A	52292382	21198	0	0
CascadePorToAonAboveFall_A	1584199	6631	0	0
CascadeSysToSysAboveFall_A	52292382	21198	0	0
CascadeSysToSysAboveRise_A	52292382	21198	0	0
ScanRstToAonRise_A	1584199	197	0	0
StablePorToAonRise_A	1584199	8416	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11083309	21198	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11083309	21198	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11083309	21198	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11083309	21198	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12550112	21198	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12550112	21198	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11083309	21198	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11083309	21198	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11083309	21198	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11083309	21198	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52292382	8416	0	0
T1	26830	3	0	0
T2	345565	39	0	0
T3	20380	2	0	0
T4	7847	1	0	0
T5	112260	109	0	0
T6	123198	27	0	0
T7	10135	2	0	0
T8	234978	27	0	0
T9	13708	1	0	0
T10	21932	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52292382	8416	0	0
T1	26830	3	0	0
T2	345565	39	0	0
T3	20380	2	0	0
T4	7847	1	0	0
T5	112260	109	0	0
T6	123198	27	0	0
T7	10135	2	0	0
T8	234978	27	0	0
T9	13708	1	0	0
T10	21932	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50199610	8416	0	0
T1	25752	3	0	0
T2	331712	39	0	0
T3	19567	2	0	0
T4	7532	1	0	0
T5	107771	109	0	0
T6	118301	27	0	0
T7	9733	2	0	0
T8	225555	27	0	0
T9	13160	1	0	0
T10	21053	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50199610	8416	0	0
T1	25752	3	0	0
T2	331712	39	0	0
T3	19567	2	0	0
T4	7532	1	0	0
T5	107771	109	0	0
T6	118301	27	0	0
T7	9733	2	0	0
T8	225555	27	0	0
T9	13160	1	0	0
T10	21053	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25100336	8416	0	0
T1	12874	3	0	0
T2	165872	39	0	0
T3	9784	2	0	0
T4	3765	1	0	0
T5	538859	109	0	0
T6	59151	27	0	0
T7	4863	2	0	0
T8	112785	27	0	0
T9	6580	1	0	0
T10	10526	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25100336	8416	0	0
T1	12874	3	0	0
T2	165872	39	0	0
T3	9784	2	0	0
T4	3765	1	0	0
T5	538859	109	0	0
T6	59151	27	0	0
T7	4863	2	0	0
T8	112785	27	0	0
T9	6580	1	0	0
T10	10526	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	8416	0	0
T1	6436	3	0	0
T2	82927	39	0	0
T3	4892	2	0	0
T4	1881	1	0	0
T5	269439	109	0	0
T6	29575	27	0	0
T7	2432	2	0	0
T8	56394	27	0	0
T9	3288	1	0	0
T10	5261	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	8416	0	0
T1	6436	3	0	0
T2	82927	39	0	0
T3	4892	2	0	0
T4	1881	1	0	0
T5	269439	109	0	0
T6	29575	27	0	0
T7	2432	2	0	0
T8	56394	27	0	0
T9	3288	1	0	0
T10	5261	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25100261	8416	0	0
T1	12874	3	0	0
T2	165850	39	0	0
T3	9785	2	0	0
T4	3765	1	0	0
T5	538858	109	0	0
T6	59138	27	0	0
T7	4863	2	0	0
T8	112789	27	0	0
T9	6579	1	0	0
T10	10527	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25100261	8416	0	0
T1	12874	3	0	0
T2	165850	39	0	0
T3	9785	2	0	0
T4	3765	1	0	0
T5	538858	109	0	0
T6	59138	27	0	0
T7	4863	2	0	0
T8	112789	27	0	0
T9	6579	1	0	0
T10	10527	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52292382	21198	0	0
T1	26830	3	0	0
T2	345565	131	0	0
T3	20380	6	0	0
T4	7847	1	0	0
T5	112260	328	0	0
T6	123198	102	0	0
T7	10135	6	0	0
T8	234978	102	0	0
T9	13708	16	0	0
T10	21932	18	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52292382	21198	0	0
T1	26830	3	0	0
T2	345565	131	0	0
T3	20380	6	0	0
T4	7847	1	0	0
T5	112260	328	0	0
T6	123198	102	0	0
T7	10135	6	0	0
T8	234978	102	0	0
T9	13708	16	0	0
T10	21932	18	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584199	21198	0	0
T1	804	3	0	0
T2	10488	131	0	0
T3	611	6	0	0
T4	235	1	0	0
T5	33978	328	0	0
T6	3712	102	0	0
T7	302	6	0	0
T8	7064	102	0	0
T9	410	16	0	0
T10	656	18	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584199	21198	0	0
T1	804	3	0	0
T2	10488	131	0	0
T3	611	6	0	0
T4	235	1	0	0
T5	33978	328	0	0
T6	3712	102	0	0
T7	302	6	0	0
T8	7064	102	0	0
T9	410	16	0	0
T10	656	18	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52292382	21198	0	0
T1	26830	3	0	0
T2	345565	131	0	0
T3	20380	6	0	0
T4	7847	1	0	0
T5	112260	328	0	0
T6	123198	102	0	0
T7	10135	6	0	0
T8	234978	102	0	0
T9	13708	16	0	0
T10	21932	18	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52292382	21198	0	0
T1	26830	3	0	0
T2	345565	131	0	0
T3	20380	6	0	0
T4	7847	1	0	0
T5	112260	328	0	0
T6	123198	102	0	0
T7	10135	6	0	0
T8	234978	102	0	0
T9	13708	16	0	0
T10	21932	18	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584199	6631	0	0
T1	804	3	0	0
T2	10488	15	0	0
T3	611	1	0	0
T4	235	1	0	0
T5	33978	58	0	0
T6	3712	27	0	0
T7	302	1	0	0
T8	7064	27	0	0
T9	410	1	0	0
T10	656	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52292382	21198	0	0
T1	26830	3	0	0
T2	345565	131	0	0
T3	20380	6	0	0
T4	7847	1	0	0
T5	112260	328	0	0
T6	123198	102	0	0
T7	10135	6	0	0
T8	234978	102	0	0
T9	13708	16	0	0
T10	21932	18	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52292382	21198	0	0
T1	26830	3	0	0
T2	345565	131	0	0
T3	20380	6	0	0
T4	7847	1	0	0
T5	112260	328	0	0
T6	123198	102	0	0
T7	10135	6	0	0
T8	234978	102	0	0
T9	13708	16	0	0
T10	21932	18	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584199	197	0	0
T2	10488	1	0	0
T3	611	0	0	0
T4	235	0	0	0
T5	33978	7	0	0
T6	3712	0	0	0
T7	302	0	0	0
T8	7064	0	0	0
T9	410	0	0	0
T10	656	0	0	0
T11	459	0	0	0
T69	0	2	0	0
T70	0	3	0	0
T71	0	1	0	0
T72	0	4	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	3	0	0
T116	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584199	8416	0	0
T1	804	3	0	0
T2	10488	39	0	0
T3	611	2	0	0
T4	235	1	0	0
T5	33978	109	0	0
T6	3712	27	0	0
T7	302	2	0	0
T8	7064	27	0	0
T9	410	1	0	0
T10	656	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11083309	21198	0	0
T1	6210	3	0	0
T2	71419	131	0	0
T3	4506	6	0	0
T4	1816	1	0	0
T5	241875	328	0	0
T6	26151	102	0	0
T7	2286	6	0	0
T8	53242	102	0	0
T9	2212	16	0	0
T10	4002	18	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11083309	21198	0	0
T1	6210	3	0	0
T2	71419	131	0	0
T3	4506	6	0	0
T4	1816	1	0	0
T5	241875	328	0	0
T6	26151	102	0	0
T7	2286	6	0	0
T8	53242	102	0	0
T9	2212	16	0	0
T10	4002	18	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11083309	21198	0	0
T1	6210	3	0	0
T2	71419	131	0	0
T3	4506	6	0	0
T4	1816	1	0	0
T5	241875	328	0	0
T6	26151	102	0	0
T7	2286	6	0	0
T8	53242	102	0	0
T9	2212	16	0	0
T10	4002	18	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11083309	21198	0	0
T1	6210	3	0	0
T2	71419	131	0	0
T3	4506	6	0	0
T4	1816	1	0	0
T5	241875	328	0	0
T6	26151	102	0	0
T7	2286	6	0	0
T8	53242	102	0	0
T9	2212	16	0	0
T10	4002	18	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	21198	0	0
T1	6436	3	0	0
T2	82927	131	0	0
T3	4892	6	0	0
T4	1881	1	0	0
T5	269439	328	0	0
T6	29575	102	0	0
T7	2432	6	0	0
T8	56394	102	0	0
T9	3288	16	0	0
T10	5261	18	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12550112	21198	0	0
T1	6436	3	0	0
T2	82927	131	0	0
T3	4892	6	0	0
T4	1881	1	0	0
T5	269439	328	0	0
T6	29575	102	0	0
T7	2432	6	0	0
T8	56394	102	0	0
T9	3288	16	0	0
T10	5261	18	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11083309	21198	0	0
T1	6210	3	0	0
T2	71419	131	0	0
T3	4506	6	0	0
T4	1816	1	0	0
T5	241875	328	0	0
T6	26151	102	0	0
T7	2286	6	0	0
T8	53242	102	0	0
T9	2212	16	0	0
T10	4002	18	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11083309	21198	0	0
T1	6210	3	0	0
T2	71419	131	0	0
T3	4506	6	0	0
T4	1816	1	0	0
T5	241875	328	0	0
T6	26151	102	0	0
T7	2286	6	0	0
T8	53242	102	0	0
T9	2212	16	0	0
T10	4002	18	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11083309	21198	0	0
T1	6210	3	0	0
T2	71419	131	0	0
T3	4506	6	0	0
T4	1816	1	0	0
T5	241875	328	0	0
T6	26151	102	0	0
T7	2286	6	0	0
T8	53242	102	0	0
T9	2212	16	0	0
T10	4002	18	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11083309	21198	0	0
T1	6210	3	0	0
T2	71419	131	0	0
T3	4506	6	0	0
T4	1816	1	0	0
T5	241875	328	0	0
T6	26151	102	0	0
T7	2286	6	0	0
T8	53242	102	0	0
T9	2212	16	0	0
T10	4002	18	0	0