Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	598390	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

357306

1

T1

6

T2

1072

T3

121

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	509700	1			T2	1500		T3	162		T4	371
values[0x0]	223105	1			T1	8		T2	837		T3	82
values[0x1]	222891	1			T1	6		T2	863		T3	85

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	502328	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

453368

1

T1

6

T2

1422

T3

153

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3636	1			T2	5		T3	1		T5	93
valid_sources[0x01]	3788	1			T2	3		T5	73		T6	5
valid_sources[0x02]	3393	1			T2	13		T3	2		T5	67
valid_sources[0x03]	3311	1			T2	12		T3	5		T5	74
valid_sources[0x04]	4373	1			T2	14		T5	61		T6	6
valid_sources[0x05]	3384	1			T2	13		T5	77		T6	1
valid_sources[0x06]	3570	1			T2	6		T5	67		T6	3
valid_sources[0x07]	3041	1			T2	5		T5	71		T6	3
valid_sources[0x08]	4343	1			T2	7		T5	60		T6	1
valid_sources[0x09]	3201	1			T2	8		T3	2		T5	88
valid_sources[0x0a]	3255	1			T2	17		T3	1		T5	93
valid_sources[0x0b]	3309	1			T2	9		T3	1		T5	68
valid_sources[0x0c]	3762	1			T2	14		T3	3		T5	80
valid_sources[0x0d]	3747	1			T2	11		T5	62		T6	6
valid_sources[0x0e]	3955	1			T2	17		T3	1		T5	66
valid_sources[0x0f]	3411	1			T2	9		T5	79		T6	2
valid_sources[0x10]	3694	1			T2	25		T5	63		T6	4
valid_sources[0x11]	3672	1			T1	1		T2	11		T3	2
valid_sources[0x12]	5391	1			T2	2		T3	1		T5	77
valid_sources[0x13]	4433	1			T2	9		T5	62		T6	3
valid_sources[0x14]	4259	1			T2	5		T5	53		T6	1
valid_sources[0x15]	4032	1			T2	7		T5	58		T6	8
valid_sources[0x16]	3165	1			T5	90		T6	4		T12	4
valid_sources[0x17]	3969	1			T2	21		T5	57		T6	2
valid_sources[0x18]	4424	1			T2	32		T3	7		T5	67
valid_sources[0x19]	4026	1			T2	20		T3	3		T5	64
valid_sources[0x1a]	3394	1			T2	14		T5	82		T6	2
valid_sources[0x1b]	3871	1			T2	15		T3	2		T5	77
valid_sources[0x1c]	5365	1			T2	12		T3	2		T5	84
valid_sources[0x1d]	3979	1			T3	3		T5	81		T6	9
valid_sources[0x1e]	3311	1			T2	6		T3	3		T5	75
valid_sources[0x1f]	5205	1			T2	26		T5	61		T6	1
valid_sources[0x20]	4495	1			T2	12		T3	3		T5	75
valid_sources[0x21]	3837	1			T2	7		T3	1		T5	63
valid_sources[0x22]	3653	1			T2	25		T3	1		T5	84
valid_sources[0x23]	3163	1			T2	10		T5	70		T6	7
valid_sources[0x24]	2884	1			T2	10		T5	88		T6	3
valid_sources[0x25]	3441	1			T2	25		T5	95		T6	1
valid_sources[0x26]	3810	1			T2	17		T3	3		T5	64
valid_sources[0x27]	3081	1			T2	11		T3	2		T5	83
valid_sources[0x28]	3080	1			T2	10		T5	78		T6	5
valid_sources[0x29]	4258	1			T2	5		T5	70		T6	5
valid_sources[0x2a]	3169	1			T2	12		T3	2		T5	72
valid_sources[0x2b]	3396	1			T2	3		T3	1		T5	68
valid_sources[0x2c]	3577	1			T2	9		T5	93		T6	5
valid_sources[0x2d]	3005	1			T2	8		T3	2		T5	81
valid_sources[0x2e]	3478	1			T2	13		T3	1		T5	52
valid_sources[0x2f]	3312	1			T2	17		T5	72		T6	3
valid_sources[0x30]	4145	1			T2	22		T5	73		T6	5
valid_sources[0x31]	4172	1			T2	8		T5	60		T6	5
valid_sources[0x32]	3374	1			T2	28		T3	3		T5	76
valid_sources[0x33]	3238	1			T2	15		T3	6		T5	77
valid_sources[0x34]	3820	1			T2	15		T3	4		T5	47
valid_sources[0x35]	4448	1			T2	18		T5	86		T6	5
valid_sources[0x36]	4700	1			T2	12		T3	2		T5	67
valid_sources[0x37]	3178	1			T2	30		T3	3		T5	81
valid_sources[0x38]	3829	1			T2	21		T5	68		T6	7
valid_sources[0x39]	3299	1			T2	5		T5	54		T6	5
valid_sources[0x3a]	3166	1			T2	10		T5	64		T6	4
valid_sources[0x3b]	3661	1			T2	30		T3	3		T5	83
valid_sources[0x3c]	2866	1			T2	4		T3	5		T5	86
valid_sources[0x3d]	3531	1			T2	17		T3	1		T5	64
valid_sources[0x3e]	3190	1			T1	2		T2	7		T5	66
valid_sources[0x3f]	3370	1			T2	10		T5	92		T6	1
valid_sources[0x40]	3949	1			T1	1		T2	11		T5	84
valid_sources[0x41]	4937	1			T2	10		T5	63		T12	59
valid_sources[0x42]	3148	1			T2	6		T3	1		T5	91
valid_sources[0x43]	3811	1			T2	27		T5	65		T6	6
valid_sources[0x44]	3204	1			T2	11		T3	4		T5	85
valid_sources[0x45]	3619	1			T2	4		T5	73		T6	4
valid_sources[0x46]	3759	1			T2	21		T5	80		T6	2
valid_sources[0x47]	4185	1			T2	9		T3	3		T5	74
valid_sources[0x48]	3117	1			T2	15		T5	98		T6	3
valid_sources[0x49]	3211	1			T2	20		T3	1		T5	67
valid_sources[0x4a]	4717	1			T2	13		T5	68		T6	4
valid_sources[0x4b]	4378	1			T2	14		T3	2		T5	58
valid_sources[0x4c]	2986	1			T2	3		T3	4		T5	71
valid_sources[0x4d]	3329	1			T2	6		T5	82		T6	8
valid_sources[0x4e]	3293	1			T2	12		T5	92		T6	7
valid_sources[0x4f]	3276	1			T2	13		T3	2		T5	75
valid_sources[0x50]	4089	1			T2	12		T3	3		T5	77
valid_sources[0x51]	3138	1			T2	16		T5	67		T6	6
valid_sources[0x52]	4322	1			T2	20		T5	80		T6	2
valid_sources[0x53]	5310	1			T2	14		T3	1		T5	83
valid_sources[0x54]	3482	1			T2	2		T3	2		T5	76
valid_sources[0x55]	4414	1			T2	8		T3	2		T5	102
valid_sources[0x56]	2842	1			T2	9		T3	1		T5	79
valid_sources[0x57]	2930	1			T2	5		T5	56		T6	4
valid_sources[0x58]	3106	1			T2	2		T3	2		T5	63
valid_sources[0x59]	3149	1			T2	22		T3	3		T5	64
valid_sources[0x5a]	3161	1			T2	8		T5	73		T6	2
valid_sources[0x5b]	3274	1			T2	11		T3	4		T5	63
valid_sources[0x5c]	5190	1			T2	9		T5	67		T6	3
valid_sources[0x5d]	3895	1			T2	20		T4	696		T5	63
valid_sources[0x5e]	3470	1			T2	10		T5	97		T6	3
valid_sources[0x5f]	3892	1			T2	17		T5	74		T6	2
valid_sources[0x60]	3353	1			T2	10		T5	60		T6	8
valid_sources[0x61]	5515	1			T3	4		T5	58		T6	4
valid_sources[0x62]	3429	1			T2	3		T3	1		T5	77
valid_sources[0x63]	3132	1			T2	8		T3	1		T5	80
valid_sources[0x64]	3940	1			T2	4		T3	3		T5	56
valid_sources[0x65]	3452	1			T2	11		T3	1		T5	69
valid_sources[0x66]	3485	1			T2	27		T3	2		T5	64
valid_sources[0x67]	3131	1			T2	17		T3	1		T5	57
valid_sources[0x68]	4221	1			T2	29		T3	2		T5	57
valid_sources[0x69]	3325	1			T2	35		T3	1		T5	72
valid_sources[0x6a]	3481	1			T2	9		T3	2		T5	65
valid_sources[0x6b]	4189	1			T2	22		T3	3		T5	75
valid_sources[0x6c]	3175	1			T2	9		T3	1		T5	62
valid_sources[0x6d]	4590	1			T2	2		T5	71		T6	2
valid_sources[0x6e]	3227	1			T2	9		T3	4		T5	65
valid_sources[0x6f]	3128	1			T2	5		T3	2		T5	68
valid_sources[0x70]	3417	1			T2	2		T5	57		T6	2
valid_sources[0x71]	4764	1			T2	11		T3	1		T5	83
valid_sources[0x72]	5043	1			T2	5		T5	67		T6	9
valid_sources[0x73]	3479	1			T2	18		T3	2		T5	76
valid_sources[0x74]	3748	1			T2	6		T5	65		T6	4
valid_sources[0x75]	5802	1			T1	1		T2	10		T3	3
valid_sources[0x76]	3660	1			T2	20		T5	63		T6	1
valid_sources[0x77]	3515	1			T2	3		T3	1		T5	54
valid_sources[0x78]	3372	1			T2	37		T3	2		T5	80
valid_sources[0x79]	6388	1			T1	1		T2	23		T3	2
valid_sources[0x7a]	3666	1			T2	22		T5	79		T6	4
valid_sources[0x7b]	3589	1			T2	19		T5	75		T6	1
valid_sources[0x7c]	3414	1			T2	13		T5	74		T6	3
valid_sources[0x7d]	3821	1			T2	12		T3	3		T5	59
valid_sources[0x7e]	4680	1			T2	23		T5	64		T6	4
valid_sources[0x7f]	3744	1			T2	20		T3	3		T5	89
valid_sources[0x80]	3497	1			T2	6		T5	92		T6	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

238785

1

T2

674

T3

87

T4

183

values[0x0]

all_enables

biggest_size

77350

1

T1

4

T2

254

T3

26

values[0x1]

all_enables

biggest_size

41171

1

T1

2

T2

144

T3

8