Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T5

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12613369	13767	0	0
gen_assertions[0].RstEnOn_A	12613369	1155	0	0
gen_assertions[0].RstNOff_A	12613369	13767	0	0
gen_assertions[0].RstNOn_A	12613369	1155	0	0
gen_assertions[1].RstEnOff_A	50452577	12594	0	0
gen_assertions[1].RstEnOn_A	50452577	1079	0	0
gen_assertions[1].RstNOff_A	50452577	12594	0	0
gen_assertions[1].RstNOn_A	50452577	1079	0	0
gen_assertions[2].RstEnOff_A	25227140	12675	0	0
gen_assertions[2].RstEnOn_A	25227140	1109	0	0
gen_assertions[2].RstNOff_A	25227140	12675	0	0
gen_assertions[2].RstNOn_A	25227140	1109	0	0
gen_assertions[3].RstEnOff_A	25227334	12684	0	0
gen_assertions[3].RstEnOn_A	25227334	1099	0	0
gen_assertions[3].RstNOff_A	25227334	12684	0	0
gen_assertions[3].RstNOn_A	25227334	1099	0	0
gen_assertions[4].RstEnOff_A	1592852	21350	0	0
gen_assertions[4].RstEnOn_A	1592852	1171	0	0
gen_assertions[4].RstNOff_A	1592852	21350	0	0
gen_assertions[4].RstNOn_A	1592852	1171	0	0
gen_assertions[5].RstEnOff_A	12613369	14009	0	0
gen_assertions[5].RstEnOn_A	12613369	1233	0	0
gen_assertions[5].RstNOff_A	12613369	14009	0	0
gen_assertions[5].RstNOn_A	12613369	1233	0	0
gen_assertions[6].RstEnOff_A	12613369	14051	0	0
gen_assertions[6].RstEnOn_A	12613369	1282	0	0
gen_assertions[6].RstNOff_A	12613369	14051	0	0
gen_assertions[6].RstNOn_A	12613369	1282	0	0
gen_assertions[7].RstEnOff_A	12613369	14058	0	0
gen_assertions[7].RstEnOn_A	12613369	1284	0	0
gen_assertions[7].RstNOff_A	12613369	14058	0	0
gen_assertions[7].RstNOn_A	12613369	1284	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	13767	0	0
T2	29233	75	0	0
T3	6343	18	0	0
T4	8791	1	0	0
T5	140695	248	0	0
T6	12048	7	0	0
T7	3005	4	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	0	150	0	0
T13	0	75	0	0
T14	0	172	0	0
T23	0	32	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	1155	0	0
T3	6343	2	0	0
T4	8791	1	0	0
T5	140695	14	0	0
T6	12048	7	0	0
T7	3005	0	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	0	15	0	0
T14	0	7	0	0
T15	5845	0	0	0
T24	0	2	0	0
T43	0	6	0	0
T72	0	2	0	0
T73	0	14	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	13767	0	0
T2	29233	75	0	0
T3	6343	18	0	0
T4	8791	1	0	0
T5	140695	248	0	0
T6	12048	7	0	0
T7	3005	4	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	0	150	0	0
T13	0	75	0	0
T14	0	172	0	0
T23	0	32	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	1155	0	0
T3	6343	2	0	0
T4	8791	1	0	0
T5	140695	14	0	0
T6	12048	7	0	0
T7	3005	0	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	0	15	0	0
T14	0	7	0	0
T15	5845	0	0	0
T24	0	2	0	0
T43	0	6	0	0
T72	0	2	0	0
T73	0	14	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50452577	12594	0	0
T2	116936	67	0	0
T3	25377	18	0	0
T4	35167	1	0	0
T5	562698	228	0	0
T6	48193	7	0	0
T7	12024	3	0	0
T8	23283	0	0	0
T9	19405	0	0	0
T10	13607	0	0	0
T11	8911	0	0	0
T12	0	147	0	0
T13	0	69	0	0
T14	0	160	0	0
T23	0	28	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50452577	1079	0	0
T4	35167	1	0	0
T5	562698	20	0	0
T6	48193	7	0	0
T7	12024	0	0	0
T8	23283	0	0	0
T9	19405	0	0	0
T10	13607	0	0	0
T11	8911	0	0	0
T12	360204	20	0	0
T14	0	5	0	0
T15	23396	0	0	0
T24	0	2	0	0
T43	0	9	0	0
T73	0	15	0	0
T74	0	22	0	0
T75	0	10	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50452577	12594	0	0
T2	116936	67	0	0
T3	25377	18	0	0
T4	35167	1	0	0
T5	562698	228	0	0
T6	48193	7	0	0
T7	12024	3	0	0
T8	23283	0	0	0
T9	19405	0	0	0
T10	13607	0	0	0
T11	8911	0	0	0
T12	0	147	0	0
T13	0	69	0	0
T14	0	160	0	0
T23	0	28	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50452577	1079	0	0
T4	35167	1	0	0
T5	562698	20	0	0
T6	48193	7	0	0
T7	12024	0	0	0
T8	23283	0	0	0
T9	19405	0	0	0
T10	13607	0	0	0
T11	8911	0	0	0
T12	360204	20	0	0
T14	0	5	0	0
T15	23396	0	0	0
T24	0	2	0	0
T43	0	9	0	0
T73	0	15	0	0
T74	0	22	0	0
T75	0	10	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25227140	12675	0	0
T2	58470	67	0	0
T3	12689	18	0	0
T4	17583	3	0	0
T5	281362	227	0	0
T6	24096	9	0	0
T7	6010	4	0	0
T8	11642	0	0	0
T9	9701	0	0	0
T10	6803	0	0	0
T11	4455	0	0	0
T12	0	147	0	0
T13	0	69	0	0
T14	0	155	0	0
T23	0	28	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25227140	1109	0	0
T4	17583	3	0	0
T5	281362	20	0	0
T6	24096	9	0	0
T7	6010	1	0	0
T8	11642	0	0	0
T9	9701	0	0	0
T10	6803	0	0	0
T11	4455	0	0	0
T12	180095	21	0	0
T15	11697	0	0	0
T24	0	3	0	0
T43	0	9	0	0
T73	0	14	0	0
T74	0	23	0	0
T75	0	11	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25227140	12675	0	0
T2	58470	67	0	0
T3	12689	18	0	0
T4	17583	3	0	0
T5	281362	227	0	0
T6	24096	9	0	0
T7	6010	4	0	0
T8	11642	0	0	0
T9	9701	0	0	0
T10	6803	0	0	0
T11	4455	0	0	0
T12	0	147	0	0
T13	0	69	0	0
T14	0	155	0	0
T23	0	28	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25227140	1109	0	0
T4	17583	3	0	0
T5	281362	20	0	0
T6	24096	9	0	0
T7	6010	1	0	0
T8	11642	0	0	0
T9	9701	0	0	0
T10	6803	0	0	0
T11	4455	0	0	0
T12	180095	21	0	0
T15	11697	0	0	0
T24	0	3	0	0
T43	0	9	0	0
T73	0	14	0	0
T74	0	23	0	0
T75	0	11	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25227334	12684	0	0
T2	58463	67	0	0
T3	12688	18	0	0
T4	17583	4	0	0
T5	281354	226	0	0
T6	24097	9	0	0
T7	6011	3	0	0
T8	11638	0	0	0
T9	9701	0	0	0
T10	6803	0	0	0
T11	4455	0	0	0
T12	0	146	0	0
T13	0	69	0	0
T14	0	161	0	0
T23	0	28	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25227334	1099	0	0
T4	17583	4	0	0
T5	281354	17	0	0
T6	24097	9	0	0
T7	6011	0	0	0
T8	11638	0	0	0
T9	9701	0	0	0
T10	6803	0	0	0
T11	4455	0	0	0
T12	180127	20	0	0
T14	0	6	0	0
T15	11693	0	0	0
T24	0	3	0	0
T43	0	11	0	0
T73	0	13	0	0
T74	0	25	0	0
T75	0	12	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25227334	12684	0	0
T2	58463	67	0	0
T3	12688	18	0	0
T4	17583	4	0	0
T5	281354	226	0	0
T6	24097	9	0	0
T7	6011	3	0	0
T8	11638	0	0	0
T9	9701	0	0	0
T10	6803	0	0	0
T11	4455	0	0	0
T12	0	146	0	0
T13	0	69	0	0
T14	0	161	0	0
T23	0	28	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25227334	1099	0	0
T4	17583	4	0	0
T5	281354	17	0	0
T6	24097	9	0	0
T7	6011	0	0	0
T8	11638	0	0	0
T9	9701	0	0	0
T10	6803	0	0	0
T11	4455	0	0	0
T12	180127	20	0	0
T14	0	6	0	0
T15	11693	0	0	0
T24	0	3	0	0
T43	0	11	0	0
T73	0	13	0	0
T74	0	25	0	0
T75	0	12	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592852	21350	0	0
T1	183	1	0	0
T2	3669	75	0	0
T3	791	19	0	0
T4	1097	6	0	0
T5	18142	363	0	0
T6	1504	11	0	0
T7	375	7	0	0
T8	729	3	0	0
T9	605	2	0	0
T10	423	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592852	1171	0	0
T4	1097	5	0	0
T5	18142	23	0	0
T6	1504	10	0	0
T7	375	1	0	0
T8	729	0	0	0
T9	605	0	0	0
T10	423	0	0	0
T11	278	0	0	0
T12	11469	23	0	0
T14	0	6	0	0
T15	732	0	0	0
T24	0	6	0	0
T43	0	11	0	0
T73	0	15	0	0
T74	0	26	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592852	21350	0	0
T1	183	1	0	0
T2	3669	75	0	0
T3	791	19	0	0
T4	1097	6	0	0
T5	18142	363	0	0
T6	1504	11	0	0
T7	375	7	0	0
T8	729	3	0	0
T9	605	2	0	0
T10	423	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592852	1171	0	0
T4	1097	5	0	0
T5	18142	23	0	0
T6	1504	10	0	0
T7	375	1	0	0
T8	729	0	0	0
T9	605	0	0	0
T10	423	0	0	0
T11	278	0	0	0
T12	11469	23	0	0
T14	0	6	0	0
T15	732	0	0	0
T24	0	6	0	0
T43	0	11	0	0
T73	0	15	0	0
T74	0	26	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	14009	0	0
T2	29233	75	0	0
T3	6343	18	0	0
T4	8791	6	0	0
T5	140695	250	0	0
T6	12048	10	0	0
T7	3005	5	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	0	155	0	0
T13	0	75	0	0
T14	0	170	0	0
T23	0	32	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	1233	0	0
T4	8791	6	0	0
T5	140695	18	0	0
T6	12048	10	0	0
T7	3005	1	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	90060	21	0	0
T14	0	5	0	0
T15	5845	0	0	0
T24	0	6	0	0
T43	0	10	0	0
T73	0	14	0	0
T76	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	14009	0	0
T2	29233	75	0	0
T3	6343	18	0	0
T4	8791	6	0	0
T5	140695	250	0	0
T6	12048	10	0	0
T7	3005	5	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	0	155	0	0
T13	0	75	0	0
T14	0	170	0	0
T23	0	32	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	1233	0	0
T4	8791	6	0	0
T5	140695	18	0	0
T6	12048	10	0	0
T7	3005	1	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	90060	21	0	0
T14	0	5	0	0
T15	5845	0	0	0
T24	0	6	0	0
T43	0	10	0	0
T73	0	14	0	0
T76	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	14051	0	0
T2	29233	75	0	0
T3	6343	18	0	0
T4	8791	7	0	0
T5	140695	253	0	0
T6	12048	12	0	0
T7	3005	4	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	0	155	0	0
T13	0	75	0	0
T14	0	172	0	0
T23	0	32	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	1282	0	0
T4	8791	7	0	0
T5	140695	21	0	0
T6	12048	12	0	0
T7	3005	0	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	90060	19	0	0
T14	0	7	0	0
T15	5845	0	0	0
T24	0	8	0	0
T43	0	14	0	0
T73	0	12	0	0
T74	0	28	0	0
T75	0	12	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	14051	0	0
T2	29233	75	0	0
T3	6343	18	0	0
T4	8791	7	0	0
T5	140695	253	0	0
T6	12048	12	0	0
T7	3005	4	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	0	155	0	0
T13	0	75	0	0
T14	0	172	0	0
T23	0	32	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	1282	0	0
T4	8791	7	0	0
T5	140695	21	0	0
T6	12048	12	0	0
T7	3005	0	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	90060	19	0	0
T14	0	7	0	0
T15	5845	0	0	0
T24	0	8	0	0
T43	0	14	0	0
T73	0	12	0	0
T74	0	28	0	0
T75	0	12	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	14058	0	0
T2	29233	75	0	0
T3	6343	18	0	0
T4	8791	7	0	0
T5	140695	252	0	0
T6	12048	13	0	0
T7	3005	4	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	0	154	0	0
T13	0	75	0	0
T14	0	169	0	0
T23	0	32	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	1284	0	0
T4	8791	7	0	0
T5	140695	19	0	0
T6	12048	13	0	0
T7	3005	0	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	90060	18	0	0
T14	0	4	0	0
T15	5845	0	0	0
T24	0	8	0	0
T43	0	15	0	0
T73	0	10	0	0
T74	0	21	0	0
T75	0	12	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	14058	0	0
T2	29233	75	0	0
T3	6343	18	0	0
T4	8791	7	0	0
T5	140695	252	0	0
T6	12048	13	0	0
T7	3005	4	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	0	154	0	0
T13	0	75	0	0
T14	0	169	0	0
T23	0	32	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	1284	0	0
T4	8791	7	0	0
T5	140695	19	0	0
T6	12048	13	0	0
T7	3005	0	0	0
T8	5820	0	0	0
T9	4850	0	0	0
T10	3400	0	0	0
T11	2227	0	0	0
T12	90060	18	0	0
T14	0	4	0	0
T15	5845	0	0	0
T24	0	8	0	0
T43	0	15	0	0
T73	0	10	0	0
T74	0	21	0	0
T75	0	12	0	0