Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11968957	6507	0	0
alert_regwen_rd_A	11968957	3927	0	0
cpu_regwen_rd_A	11968957	3860	0	0
sw_rst_ctrl_n_0_rd_A	11968957	7820	0	0
sw_rst_ctrl_n_1_rd_A	11968957	7877	0	0
sw_rst_ctrl_n_2_rd_A	11968957	7891	0	0
sw_rst_ctrl_n_3_rd_A	11968957	8084	0	0
sw_rst_ctrl_n_4_rd_A	11968957	7929	0	0
sw_rst_ctrl_n_5_rd_A	11968957	8058	0	0
sw_rst_ctrl_n_6_rd_A	11968957	8133	0	0
sw_rst_ctrl_n_7_rd_A	11968957	8235	0	0
sw_rst_regwen_0_rd_A	11968957	4286	0	0
sw_rst_regwen_1_rd_A	11968957	4355	0	0
sw_rst_regwen_2_rd_A	11968957	4336	0	0
sw_rst_regwen_3_rd_A	11968957	4563	0	0
sw_rst_regwen_4_rd_A	11968957	4603	0	0
sw_rst_regwen_5_rd_A	11968957	4350	0	0
sw_rst_regwen_6_rd_A	11968957	4404	0	0
sw_rst_regwen_7_rd_A	11968957	4474	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	6507	0	0
T51	32804	3	0	0
T53	5784	700	0	0
T54	5927	184	0	0
T55	2903	32	0	0
T61	11234	2	0	0
T77	2423	86	0	0
T78	4685	13	0	0
T79	3059	13	0	0
T80	11826	519	0	0
T81	4510	25	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	3927	0	0
T16	4571	0	0	0
T45	43053	58	0	0
T46	5467	0	0	0
T59	4500	0	0	0
T68	0	21	0	0
T71	30226	0	0	0
T72	3292	0	0	0
T73	46956	0	0	0
T74	0	127	0	0
T75	0	29	0	0
T76	2470	0	0	0
T83	16692	0	0	0
T88	0	67	0	0
T90	0	71	0	0
T116	0	73	0	0
T117	0	43	0	0
T118	0	20	0	0
T119	0	45	0	0
T120	5464	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	3860	0	0
T16	4571	0	0	0
T45	43053	71	0	0
T46	5467	0	0	0
T59	4500	0	0	0
T68	0	16	0	0
T71	30226	0	0	0
T72	3292	0	0	0
T73	46956	0	0	0
T74	0	149	0	0
T75	0	17	0	0
T76	2470	0	0	0
T83	16692	0	0	0
T88	0	54	0	0
T90	0	64	0	0
T116	0	76	0	0
T117	0	40	0	0
T118	0	28	0	0
T119	0	48	0	0
T120	5464	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	7820	0	0
T3	5131	63	0	0
T4	8772	118	0	0
T5	109884	0	0	0
T6	12029	185	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T15	5109	0	0	0
T45	0	44	0	0
T72	0	24	0	0
T74	0	511	0	0
T75	0	109	0	0
T121	0	32	0	0
T122	0	13	0	0
T123	0	61	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	7877	0	0
T3	5131	65	0	0
T4	8772	145	0	0
T5	109884	0	0	0
T6	12029	168	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T15	5109	0	0	0
T45	0	61	0	0
T72	0	25	0	0
T74	0	431	0	0
T75	0	96	0	0
T121	0	40	0	0
T122	0	8	0	0
T123	0	68	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	7891	0	0
T3	5131	58	0	0
T4	8772	108	0	0
T5	109884	0	0	0
T6	12029	179	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T15	5109	0	0	0
T45	0	68	0	0
T72	0	19	0	0
T74	0	471	0	0
T75	0	110	0	0
T121	0	49	0	0
T122	0	6	0	0
T123	0	91	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	8084	0	0
T3	5131	61	0	0
T4	8772	151	0	0
T5	109884	0	0	0
T6	12029	157	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T15	5109	0	0	0
T45	0	59	0	0
T72	0	40	0	0
T74	0	497	0	0
T75	0	119	0	0
T121	0	59	0	0
T122	0	5	0	0
T123	0	81	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	7929	0	0
T3	5131	68	0	0
T4	8772	123	0	0
T5	109884	0	0	0
T6	12029	210	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T15	5109	0	0	0
T45	0	70	0	0
T72	0	28	0	0
T74	0	518	0	0
T75	0	126	0	0
T121	0	27	0	0
T122	0	11	0	0
T123	0	90	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	8058	0	0
T3	5131	49	0	0
T4	8772	109	0	0
T5	109884	0	0	0
T6	12029	171	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T15	5109	0	0	0
T45	0	70	0	0
T72	0	17	0	0
T74	0	421	0	0
T75	0	122	0	0
T121	0	34	0	0
T122	0	10	0	0
T123	0	88	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	8133	0	0
T3	5131	64	0	0
T4	8772	121	0	0
T5	109884	0	0	0
T6	12029	189	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T15	5109	0	0	0
T45	0	65	0	0
T72	0	23	0	0
T74	0	484	0	0
T75	0	110	0	0
T121	0	28	0	0
T122	0	18	0	0
T123	0	78	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	8235	0	0
T3	5131	62	0	0
T4	8772	138	0	0
T5	109884	0	0	0
T6	12029	212	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T15	5109	0	0	0
T45	0	60	0	0
T72	0	29	0	0
T74	0	484	0	0
T75	0	111	0	0
T121	0	54	0	0
T122	0	13	0	0
T123	0	59	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	4286	0	0
T4	8772	35	0	0
T5	109884	0	0	0
T6	12029	26	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T12	73513	0	0	0
T15	5109	0	0	0
T45	0	62	0	0
T66	0	2	0	0
T68	0	29	0	0
T74	0	159	0	0
T75	0	20	0	0
T123	0	24	0	0
T124	0	3	0	0
T125	0	14	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	4355	0	0
T4	8772	32	0	0
T5	109884	0	0	0
T6	12029	39	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T12	73513	0	0	0
T15	5109	0	0	0
T45	0	80	0	0
T66	0	4	0	0
T68	0	20	0	0
T74	0	105	0	0
T75	0	26	0	0
T123	0	8	0	0
T124	0	3	0	0
T125	0	30	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	4336	0	0
T4	8772	26	0	0
T5	109884	0	0	0
T6	12029	25	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T12	73513	0	0	0
T15	5109	0	0	0
T45	0	61	0	0
T66	0	6	0	0
T68	0	23	0	0
T74	0	144	0	0
T75	0	10	0	0
T122	0	2	0	0
T123	0	15	0	0
T124	0	11	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	4563	0	0
T4	8772	28	0	0
T5	109884	0	0	0
T6	12029	24	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T12	73513	0	0	0
T15	5109	0	0	0
T45	0	73	0	0
T66	0	3	0	0
T68	0	36	0	0
T74	0	136	0	0
T75	0	14	0	0
T122	0	8	0	0
T123	0	21	0	0
T124	0	11	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	4603	0	0
T4	8772	28	0	0
T5	109884	0	0	0
T6	12029	54	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T12	73513	0	0	0
T15	5109	0	0	0
T45	0	65	0	0
T66	0	8	0	0
T68	0	17	0	0
T74	0	112	0	0
T75	0	26	0	0
T122	0	13	0	0
T123	0	15	0	0
T124	0	13	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	4350	0	0
T4	8772	27	0	0
T5	109884	0	0	0
T6	12029	40	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T12	73513	0	0	0
T15	5109	0	0	0
T45	0	51	0	0
T68	0	27	0	0
T74	0	133	0	0
T75	0	18	0	0
T122	0	9	0	0
T123	0	30	0	0
T124	0	4	0	0
T125	0	24	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	4404	0	0
T4	8772	44	0	0
T5	109884	0	0	0
T6	12029	40	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T12	73513	0	0	0
T15	5109	0	0	0
T45	0	53	0	0
T66	0	3	0	0
T68	0	36	0	0
T74	0	132	0	0
T75	0	29	0	0
T122	0	1	0	0
T123	0	23	0	0
T124	0	3	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11968957	4474	0	0
T4	8772	21	0	0
T5	109884	0	0	0
T6	12029	23	0	0
T7	2768	0	0	0
T8	5275	0	0	0
T9	4783	0	0	0
T10	3287	0	0	0
T11	2137	0	0	0
T12	73513	0	0	0
T15	5109	0	0	0
T45	0	65	0	0
T66	0	5	0	0
T68	0	41	0	0
T74	0	155	0	0
T75	0	31	0	0
T122	0	10	0	0
T123	0	27	0	0
T124	0	7	0	0