Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T12
0	1	Covered	T5,T12,T14
1	0	Covered	T5,T7,T12

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T8
1	0	Covered	T5,T7,T12
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52556536	8712	0	0
CascadeEffAonToRstPorAboveRise_A	52556536	8712	0	0
CascadeEffAonToRstPorIoAboveFall_A	50452577	8712	0	0
CascadeEffAonToRstPorIoAboveRise_A	50452577	8712	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25227140	8712	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25227140	8712	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12613369	8712	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12613369	8712	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25227334	8712	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25227334	8712	0	0
CascadeLcToLcAboveFall_A	52556536	21528	0	0
CascadeLcToLcAboveRise_A	52556536	21528	0	0
CascadeLcToLcAonAboveFall_A	1592852	21528	0	0
CascadeLcToLcAonAboveRise_A	1592852	21528	0	0
CascadeLcToLcShadowedAboveFall_A	52556536	21528	0	0
CascadeLcToLcShadowedAboveRise_A	52556536	21528	0	0
CascadePorToAonAboveFall_A	1592852	6936	0	0
CascadeSysToSysAboveFall_A	52556536	21528	0	0
CascadeSysToSysAboveRise_A	52556536	21528	0	0
ScanRstToAonRise_A	1592852	210	0	0
StablePorToAonRise_A	1592852	8712	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11228838	21528	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11228838	21528	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11228838	21528	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11228838	21528	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12613369	21528	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12613369	21528	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11228838	21528	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11228838	21528	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11228838	21528	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11228838	21528	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52556536	8712	0	0
T1	6170	1	0	0
T2	121813	27	0	0
T3	26435	1	0	0
T4	36634	1	0	0
T5	586218	118	0	0
T6	50202	1	0	0
T7	12522	2	0	0
T8	24256	8	0	0
T9	20214	2	0	0
T10	14175	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52556536	8712	0	0
T1	6170	1	0	0
T2	121813	27	0	0
T3	26435	1	0	0
T4	36634	1	0	0
T5	586218	118	0	0
T6	50202	1	0	0
T7	12522	2	0	0
T8	24256	8	0	0
T9	20214	2	0	0
T10	14175	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50452577	8712	0	0
T1	5922	1	0	0
T2	116936	27	0	0
T3	25377	1	0	0
T4	35167	1	0	0
T5	562698	118	0	0
T6	48193	1	0	0
T7	12024	2	0	0
T8	23283	8	0	0
T9	19405	2	0	0
T10	13607	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50452577	8712	0	0
T1	5922	1	0	0
T2	116936	27	0	0
T3	25377	1	0	0
T4	35167	1	0	0
T5	562698	118	0	0
T6	48193	1	0	0
T7	12024	2	0	0
T8	23283	8	0	0
T9	19405	2	0	0
T10	13607	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25227140	8712	0	0
T1	2961	1	0	0
T2	58470	27	0	0
T3	12689	1	0	0
T4	17583	1	0	0
T5	281362	118	0	0
T6	24096	1	0	0
T7	6010	2	0	0
T8	11642	8	0	0
T9	9701	2	0	0
T10	6803	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25227140	8712	0	0
T1	2961	1	0	0
T2	58470	27	0	0
T3	12689	1	0	0
T4	17583	1	0	0
T5	281362	118	0	0
T6	24096	1	0	0
T7	6010	2	0	0
T8	11642	8	0	0
T9	9701	2	0	0
T10	6803	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	8712	0	0
T1	1479	1	0	0
T2	29233	27	0	0
T3	6343	1	0	0
T4	8791	1	0	0
T5	140695	118	0	0
T6	12048	1	0	0
T7	3005	2	0	0
T8	5820	8	0	0
T9	4850	2	0	0
T10	3400	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	8712	0	0
T1	1479	1	0	0
T2	29233	27	0	0
T3	6343	1	0	0
T4	8791	1	0	0
T5	140695	118	0	0
T6	12048	1	0	0
T7	3005	2	0	0
T8	5820	8	0	0
T9	4850	2	0	0
T10	3400	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25227334	8712	0	0
T1	2961	1	0	0
T2	58463	27	0	0
T3	12688	1	0	0
T4	17583	1	0	0
T5	281354	118	0	0
T6	24097	1	0	0
T7	6011	2	0	0
T8	11638	8	0	0
T9	9701	2	0	0
T10	6803	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25227334	8712	0	0
T1	2961	1	0	0
T2	58463	27	0	0
T3	12688	1	0	0
T4	17583	1	0	0
T5	281354	118	0	0
T6	24097	1	0	0
T7	6011	2	0	0
T8	11638	8	0	0
T9	9701	2	0	0
T10	6803	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52556536	21528	0	0
T1	6170	1	0	0
T2	121813	102	0	0
T3	26435	19	0	0
T4	36634	1	0	0
T5	586218	352	0	0
T6	50202	1	0	0
T7	12522	6	0	0
T8	24256	8	0	0
T9	20214	2	0	0
T10	14175	2	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52556536	21528	0	0
T1	6170	1	0	0
T2	121813	102	0	0
T3	26435	19	0	0
T4	36634	1	0	0
T5	586218	352	0	0
T6	50202	1	0	0
T7	12522	6	0	0
T8	24256	8	0	0
T9	20214	2	0	0
T10	14175	2	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592852	21528	0	0
T1	183	1	0	0
T2	3669	102	0	0
T3	791	19	0	0
T4	1097	1	0	0
T5	18142	352	0	0
T6	1504	1	0	0
T7	375	6	0	0
T8	729	8	0	0
T9	605	2	0	0
T10	423	2	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592852	21528	0	0
T1	183	1	0	0
T2	3669	102	0	0
T3	791	19	0	0
T4	1097	1	0	0
T5	18142	352	0	0
T6	1504	1	0	0
T7	375	6	0	0
T8	729	8	0	0
T9	605	2	0	0
T10	423	2	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52556536	21528	0	0
T1	6170	1	0	0
T2	121813	102	0	0
T3	26435	19	0	0
T4	36634	1	0	0
T5	586218	352	0	0
T6	50202	1	0	0
T7	12522	6	0	0
T8	24256	8	0	0
T9	20214	2	0	0
T10	14175	2	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52556536	21528	0	0
T1	6170	1	0	0
T2	121813	102	0	0
T3	26435	19	0	0
T4	36634	1	0	0
T5	586218	352	0	0
T6	50202	1	0	0
T7	12522	6	0	0
T8	24256	8	0	0
T9	20214	2	0	0
T10	14175	2	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592852	6936	0	0
T1	183	1	0	0
T2	3669	27	0	0
T3	791	1	0	0
T4	1097	1	0	0
T5	18142	56	0	0
T6	1504	1	0	0
T7	375	1	0	0
T8	729	8	0	0
T9	605	18	0	0
T10	423	9	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52556536	21528	0	0
T1	6170	1	0	0
T2	121813	102	0	0
T3	26435	19	0	0
T4	36634	1	0	0
T5	586218	352	0	0
T6	50202	1	0	0
T7	12522	6	0	0
T8	24256	8	0	0
T9	20214	2	0	0
T10	14175	2	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52556536	21528	0	0
T1	6170	1	0	0
T2	121813	102	0	0
T3	26435	19	0	0
T4	36634	1	0	0
T5	586218	352	0	0
T6	50202	1	0	0
T7	12522	6	0	0
T8	24256	8	0	0
T9	20214	2	0	0
T10	14175	2	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592852	210	0	0
T5	18142	7	0	0
T6	1504	0	0	0
T7	375	0	0	0
T8	729	0	0	0
T9	605	0	0	0
T10	423	0	0	0
T11	278	0	0	0
T12	11469	3	0	0
T13	3643	0	0	0
T14	0	1	0	0
T15	732	0	0	0
T44	0	1	0	0
T71	0	2	0	0
T73	0	2	0	0
T74	0	3	0	0
T83	0	1	0	0
T85	0	6	0	0
T91	0	8	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592852	8712	0	0
T1	183	1	0	0
T2	3669	27	0	0
T3	791	1	0	0
T4	1097	1	0	0
T5	18142	118	0	0
T6	1504	1	0	0
T7	375	2	0	0
T8	729	8	0	0
T9	605	2	0	0
T10	423	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11228838	21528	0	0
T1	1461	1	0	0
T2	26013	102	0	0
T3	5131	19	0	0
T4	8772	1	0	0
T5	109884	352	0	0
T6	12029	1	0	0
T7	2768	6	0	0
T8	5275	8	0	0
T9	4783	2	0	0
T10	3287	2	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11228838	21528	0	0
T1	1461	1	0	0
T2	26013	102	0	0
T3	5131	19	0	0
T4	8772	1	0	0
T5	109884	352	0	0
T6	12029	1	0	0
T7	2768	6	0	0
T8	5275	8	0	0
T9	4783	2	0	0
T10	3287	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11228838	21528	0	0
T1	1461	1	0	0
T2	26013	102	0	0
T3	5131	19	0	0
T4	8772	1	0	0
T5	109884	352	0	0
T6	12029	1	0	0
T7	2768	6	0	0
T8	5275	8	0	0
T9	4783	2	0	0
T10	3287	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11228838	21528	0	0
T1	1461	1	0	0
T2	26013	102	0	0
T3	5131	19	0	0
T4	8772	1	0	0
T5	109884	352	0	0
T6	12029	1	0	0
T7	2768	6	0	0
T8	5275	8	0	0
T9	4783	2	0	0
T10	3287	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	21528	0	0
T1	1479	1	0	0
T2	29233	102	0	0
T3	6343	19	0	0
T4	8791	1	0	0
T5	140695	352	0	0
T6	12048	1	0	0
T7	3005	6	0	0
T8	5820	8	0	0
T9	4850	2	0	0
T10	3400	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12613369	21528	0	0
T1	1479	1	0	0
T2	29233	102	0	0
T3	6343	19	0	0
T4	8791	1	0	0
T5	140695	352	0	0
T6	12048	1	0	0
T7	3005	6	0	0
T8	5820	8	0	0
T9	4850	2	0	0
T10	3400	2	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11228838	21528	0	0
T1	1461	1	0	0
T2	26013	102	0	0
T3	5131	19	0	0
T4	8772	1	0	0
T5	109884	352	0	0
T6	12029	1	0	0
T7	2768	6	0	0
T8	5275	8	0	0
T9	4783	2	0	0
T10	3287	2	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11228838	21528	0	0
T1	1461	1	0	0
T2	26013	102	0	0
T3	5131	19	0	0
T4	8772	1	0	0
T5	109884	352	0	0
T6	12029	1	0	0
T7	2768	6	0	0
T8	5275	8	0	0
T9	4783	2	0	0
T10	3287	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11228838	21528	0	0
T1	1461	1	0	0
T2	26013	102	0	0
T3	5131	19	0	0
T4	8772	1	0	0
T5	109884	352	0	0
T6	12029	1	0	0
T7	2768	6	0	0
T8	5275	8	0	0
T9	4783	2	0	0
T10	3287	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11228838	21528	0	0
T1	1461	1	0	0
T2	26013	102	0	0
T3	5131	19	0	0
T4	8772	1	0	0
T5	109884	352	0	0
T6	12029	1	0	0
T7	2768	6	0	0
T8	5275	8	0	0
T9	4783	2	0	0
T10	3287	2	0	0