Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	608175	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

362876

1

T1

242

T2

881

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	517483	1			T1	355		T2	1386		T5	1
values[0x0]	226410	1			T1	152		T2	524		T4	2
values[0x1]	227158	1			T1	157		T2	518		T6	55

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	510733	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

460318

1

T1

296

T2

1129

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4422	1			T1	1		T2	12		T7	3
valid_sources[0x01]	2777	1			T2	13		T7	2		T8	12
valid_sources[0x02]	3909	1			T2	11		T7	1		T8	13
valid_sources[0x03]	3658	1			T1	9		T2	12		T7	4
valid_sources[0x04]	3633	1			T2	6		T7	4		T8	14
valid_sources[0x05]	5027	1			T2	10		T7	3		T8	11
valid_sources[0x06]	2701	1			T1	3		T2	13		T7	4
valid_sources[0x07]	4328	1			T2	7		T7	1		T8	9
valid_sources[0x08]	3322	1			T2	23		T7	2		T8	13
valid_sources[0x09]	3443	1			T2	14		T7	1		T8	7
valid_sources[0x0a]	3585	1			T2	9		T7	6		T8	9
valid_sources[0x0b]	3309	1			T1	5		T2	9		T7	7
valid_sources[0x0c]	2914	1			T1	2		T2	9		T7	3
valid_sources[0x0d]	2916	1			T1	3		T2	7		T7	6
valid_sources[0x0e]	6044	1			T2	8		T7	2		T8	12
valid_sources[0x0f]	3335	1			T2	15		T7	2		T8	17
valid_sources[0x10]	3539	1			T2	13		T7	7		T8	9
valid_sources[0x11]	3317	1			T1	1		T2	12		T7	5
valid_sources[0x12]	2998	1			T2	8		T7	2		T8	8
valid_sources[0x13]	6515	1			T2	5		T7	3		T8	8
valid_sources[0x14]	3192	1			T2	9		T7	2		T8	10
valid_sources[0x15]	3426	1			T1	19		T2	12		T7	2
valid_sources[0x16]	4000	1			T1	5		T2	8		T7	5
valid_sources[0x17]	3494	1			T2	8		T7	7		T8	13
valid_sources[0x18]	4746	1			T1	1		T2	5		T7	3
valid_sources[0x19]	3672	1			T2	10		T7	1		T8	18
valid_sources[0x1a]	3490	1			T2	11		T7	3		T8	11
valid_sources[0x1b]	2940	1			T2	6		T7	3		T8	8
valid_sources[0x1c]	3670	1			T2	2		T7	7		T8	12
valid_sources[0x1d]	3509	1			T2	8		T7	5		T8	13
valid_sources[0x1e]	3239	1			T1	5		T2	9		T7	1
valid_sources[0x1f]	3872	1			T2	7		T7	6		T8	14
valid_sources[0x20]	2869	1			T1	3		T2	6		T7	7
valid_sources[0x21]	4738	1			T1	16		T2	12		T7	1
valid_sources[0x22]	5471	1			T1	7		T2	10		T7	1
valid_sources[0x23]	3180	1			T2	10		T7	3		T8	10
valid_sources[0x24]	3571	1			T1	9		T2	5		T7	2
valid_sources[0x25]	3066	1			T2	5		T7	2		T8	11
valid_sources[0x26]	3702	1			T2	7		T7	3		T8	15
valid_sources[0x27]	3215	1			T1	1		T2	11		T7	2
valid_sources[0x28]	3181	1			T1	2		T2	17		T7	4
valid_sources[0x29]	4679	1			T2	10		T7	8		T8	13
valid_sources[0x2a]	3759	1			T1	5		T2	8		T7	2
valid_sources[0x2b]	4219	1			T1	13		T2	12		T7	5
valid_sources[0x2c]	4091	1			T2	9		T7	3		T8	10
valid_sources[0x2d]	3266	1			T2	19		T7	5		T8	14
valid_sources[0x2e]	3698	1			T1	4		T2	11		T7	1
valid_sources[0x2f]	2710	1			T1	1		T2	7		T7	5
valid_sources[0x30]	5320	1			T1	5		T2	9		T7	3
valid_sources[0x31]	3727	1			T2	9		T7	3		T8	9
valid_sources[0x32]	5536	1			T2	10		T7	1		T8	15
valid_sources[0x33]	3618	1			T1	3		T2	12		T7	3
valid_sources[0x34]	6662	1			T1	8		T2	13		T7	7
valid_sources[0x35]	3473	1			T2	5		T7	3		T8	9
valid_sources[0x36]	3464	1			T2	6		T7	5		T8	16
valid_sources[0x37]	3248	1			T1	16		T2	10		T7	2
valid_sources[0x38]	3121	1			T2	10		T7	2		T8	11
valid_sources[0x39]	3037	1			T2	7		T7	2		T8	11
valid_sources[0x3a]	3965	1			T1	7		T2	8		T7	7
valid_sources[0x3b]	3441	1			T1	4		T2	8		T7	4
valid_sources[0x3c]	3336	1			T2	7		T8	13		T12	59
valid_sources[0x3d]	4182	1			T1	2		T2	6		T7	2
valid_sources[0x3e]	4184	1			T2	6		T7	3		T8	12
valid_sources[0x3f]	3688	1			T1	11		T2	2		T7	1
valid_sources[0x40]	3462	1			T2	19		T7	3		T8	15
valid_sources[0x41]	3916	1			T1	3		T2	8		T8	11
valid_sources[0x42]	3488	1			T1	4		T2	10		T7	4
valid_sources[0x43]	3272	1			T1	1		T2	8		T8	14
valid_sources[0x44]	3579	1			T2	17		T7	4		T8	12
valid_sources[0x45]	4460	1			T1	1		T2	16		T7	2
valid_sources[0x46]	6699	1			T1	7		T2	9		T7	6
valid_sources[0x47]	5434	1			T1	1		T2	7		T7	1
valid_sources[0x48]	3864	1			T2	8		T7	2		T8	10
valid_sources[0x49]	3010	1			T2	11		T7	3		T8	13
valid_sources[0x4a]	3800	1			T1	4		T2	10		T7	8
valid_sources[0x4b]	3930	1			T2	9		T7	3		T8	12
valid_sources[0x4c]	3702	1			T1	1		T2	5		T7	1
valid_sources[0x4d]	4577	1			T2	15		T7	2		T8	12
valid_sources[0x4e]	3311	1			T2	8		T7	4		T8	14
valid_sources[0x4f]	3826	1			T1	14		T2	3		T7	4
valid_sources[0x50]	4028	1			T1	2		T2	7		T7	1
valid_sources[0x51]	3238	1			T2	6		T7	3		T8	12
valid_sources[0x52]	3362	1			T1	7		T2	9		T7	3
valid_sources[0x53]	3453	1			T1	11		T2	11		T7	5
valid_sources[0x54]	2885	1			T1	11		T2	13		T7	2
valid_sources[0x55]	3740	1			T1	1		T2	8		T7	3
valid_sources[0x56]	3707	1			T1	3		T2	14		T7	2
valid_sources[0x57]	2964	1			T1	1		T2	4		T7	2
valid_sources[0x58]	3961	1			T2	6		T7	2		T8	10
valid_sources[0x59]	2867	1			T2	9		T7	6		T8	13
valid_sources[0x5a]	5109	1			T1	1		T2	12		T7	7
valid_sources[0x5b]	4389	1			T2	5		T7	4		T8	9
valid_sources[0x5c]	4693	1			T2	18		T7	3		T8	8
valid_sources[0x5d]	3419	1			T1	2		T2	5		T7	1
valid_sources[0x5e]	2794	1			T1	14		T2	4		T7	3
valid_sources[0x5f]	3274	1			T1	15		T2	7		T7	1
valid_sources[0x60]	3850	1			T1	2		T2	12		T7	2
valid_sources[0x61]	5243	1			T1	3		T2	8		T7	4
valid_sources[0x62]	3261	1			T1	4		T2	11		T7	1
valid_sources[0x63]	4118	1			T1	4		T2	5		T7	3
valid_sources[0x64]	4457	1			T2	16		T7	3		T8	14
valid_sources[0x65]	5082	1			T1	2		T2	13		T7	4
valid_sources[0x66]	4754	1			T2	9		T7	4		T8	12
valid_sources[0x67]	3438	1			T1	14		T2	12		T7	4
valid_sources[0x68]	3175	1			T1	8		T2	11		T7	4
valid_sources[0x69]	5291	1			T2	12		T7	3		T8	16
valid_sources[0x6a]	3757	1			T2	9		T7	5		T8	14
valid_sources[0x6b]	3314	1			T2	8		T7	3		T8	12
valid_sources[0x6c]	3476	1			T2	7		T7	7		T8	13
valid_sources[0x6d]	3703	1			T1	1		T2	8		T7	1
valid_sources[0x6e]	3257	1			T2	14		T7	2		T8	16
valid_sources[0x6f]	3312	1			T2	16		T7	1		T8	8
valid_sources[0x70]	2747	1			T1	10		T2	9		T7	3
valid_sources[0x71]	3276	1			T2	11		T7	4		T8	11
valid_sources[0x72]	3091	1			T2	7		T7	3		T8	14
valid_sources[0x73]	2805	1			T1	8		T2	12		T7	6
valid_sources[0x74]	3254	1			T1	5		T2	19		T5	1
valid_sources[0x75]	2951	1			T2	11		T7	3		T8	12
valid_sources[0x76]	4258	1			T1	1		T2	11		T7	5
valid_sources[0x77]	4048	1			T2	4		T7	4		T8	16
valid_sources[0x78]	4574	1			T2	12		T7	4		T8	16
valid_sources[0x79]	7586	1			T2	1		T7	3		T8	9
valid_sources[0x7a]	3233	1			T1	5		T2	5		T7	5
valid_sources[0x7b]	3404	1			T2	12		T8	7		T11	2
valid_sources[0x7c]	3337	1			T1	4		T2	4		T7	4
valid_sources[0x7d]	4057	1			T1	17		T2	11		T7	3
valid_sources[0x7e]	3894	1			T1	4		T2	12		T7	3
valid_sources[0x7f]	4112	1			T1	8		T2	13		T7	6
valid_sources[0x80]	6747	1			T2	4		T7	12		T8	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

242288

1

T1

185

T2

626

T6

50

values[0x0]

all_enables

biggest_size

78543

1

T1

42

T2

168

T4

1

values[0x1]

all_enables

biggest_size

42045

1

T1

15

T2

87

T6

9