Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T9
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T10
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T10
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T10
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T10
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T10
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T10
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T10
1	0	Covered	T2,T3,T5

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12606835	13904	0	0
gen_assertions[0].RstEnOn_A	12606835	1118	0	0
gen_assertions[0].RstNOff_A	12606835	13904	0	0
gen_assertions[0].RstNOn_A	12606835	1118	0	0
gen_assertions[1].RstEnOff_A	50426463	12658	0	0
gen_assertions[1].RstEnOn_A	50426463	1078	0	0
gen_assertions[1].RstNOff_A	50426463	12658	0	0
gen_assertions[1].RstNOn_A	50426463	1078	0	0
gen_assertions[2].RstEnOff_A	25214374	12696	0	0
gen_assertions[2].RstEnOn_A	25214374	1068	0	0
gen_assertions[2].RstNOff_A	25214374	12696	0	0
gen_assertions[2].RstNOn_A	25214374	1068	0	0
gen_assertions[3].RstEnOff_A	25214129	12785	0	0
gen_assertions[3].RstEnOn_A	25214129	1152	0	0
gen_assertions[3].RstNOff_A	25214129	12785	0	0
gen_assertions[3].RstNOn_A	25214129	1152	0	0
gen_assertions[4].RstEnOff_A	1593342	21814	0	0
gen_assertions[4].RstEnOn_A	1593342	1187	0	0
gen_assertions[4].RstNOff_A	1593342	21814	0	0
gen_assertions[4].RstNOn_A	1593342	1187	0	0
gen_assertions[5].RstEnOff_A	12606835	14122	0	0
gen_assertions[5].RstEnOn_A	12606835	1210	0	0
gen_assertions[5].RstNOff_A	12606835	14122	0	0
gen_assertions[5].RstNOn_A	12606835	1210	0	0
gen_assertions[6].RstEnOff_A	12606835	14184	0	0
gen_assertions[6].RstEnOn_A	12606835	1278	0	0
gen_assertions[6].RstNOff_A	12606835	14184	0	0
gen_assertions[6].RstNOn_A	12606835	1278	0	0
gen_assertions[7].RstEnOff_A	12606835	14248	0	0
gen_assertions[7].RstEnOn_A	12606835	1331	0	0
gen_assertions[7].RstNOff_A	12606835	14248	0	0
gen_assertions[7].RstNOn_A	12606835	1331	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	13904	0	0
T1	2847	1	0	0
T2	30735	29	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	4	0	0
T7	8219	17	0	0
T8	45579	75	0	0
T9	4638	14	0	0
T10	121628	237	0	0
T11	0	12	0	0
T12	0	218	0	0
T13	0	36	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	1118	0	0
T1	2847	1	0	0
T2	30735	0	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	0	0	0
T7	8219	9	0	0
T8	45579	0	0	0
T9	4638	3	0	0
T10	121628	18	0	0
T11	0	6	0	0
T12	0	33	0	0
T23	0	4	0	0
T50	0	1	0	0
T51	0	23	0	0
T104	0	8	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	13904	0	0
T1	2847	1	0	0
T2	30735	29	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	4	0	0
T7	8219	17	0	0
T8	45579	75	0	0
T9	4638	14	0	0
T10	121628	237	0	0
T11	0	12	0	0
T12	0	218	0	0
T13	0	36	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	1118	0	0
T1	2847	1	0	0
T2	30735	0	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	0	0	0
T7	8219	9	0	0
T8	45579	0	0	0
T9	4638	3	0	0
T10	121628	18	0	0
T11	0	6	0	0
T12	0	33	0	0
T23	0	4	0	0
T50	0	1	0	0
T51	0	23	0	0
T104	0	8	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50426463	12658	0	0
T1	11395	1	0	0
T2	122928	24	0	0
T3	23322	0	0	0
T4	4954	0	0	0
T5	20083	0	0	0
T6	13980	4	0	0
T7	32867	13	0	0
T8	182287	68	0	0
T9	18551	12	0	0
T10	486426	221	0	0
T11	0	10	0	0
T12	0	202	0	0
T13	0	35	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50426463	1078	0	0
T1	11395	1	0	0
T2	122928	0	0	0
T3	23322	0	0	0
T4	4954	0	0	0
T5	20083	0	0	0
T6	13980	0	0	0
T7	32867	5	0	0
T8	182287	0	0	0
T9	18551	0	0	0
T10	486426	17	0	0
T11	0	2	0	0
T12	0	27	0	0
T23	0	6	0	0
T35	0	32	0	0
T50	0	4	0	0
T51	0	23	0	0
T104	0	8	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50426463	12658	0	0
T1	11395	1	0	0
T2	122928	24	0	0
T3	23322	0	0	0
T4	4954	0	0	0
T5	20083	0	0	0
T6	13980	4	0	0
T7	32867	13	0	0
T8	182287	68	0	0
T9	18551	12	0	0
T10	486426	221	0	0
T11	0	10	0	0
T12	0	202	0	0
T13	0	35	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50426463	1078	0	0
T1	11395	1	0	0
T2	122928	0	0	0
T3	23322	0	0	0
T4	4954	0	0	0
T5	20083	0	0	0
T6	13980	0	0	0
T7	32867	5	0	0
T8	182287	0	0	0
T9	18551	0	0	0
T10	486426	17	0	0
T11	0	2	0	0
T12	0	27	0	0
T23	0	6	0	0
T35	0	32	0	0
T50	0	4	0	0
T51	0	23	0	0
T104	0	8	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25214374	12696	0	0
T1	5696	2	0	0
T2	61469	24	0	0
T3	11667	0	0	0
T4	2477	0	0	0
T5	10042	0	0	0
T6	6991	4	0	0
T7	16439	15	0	0
T8	91160	68	0	0
T9	9275	12	0	0
T10	243248	222	0	0
T11	0	10	0	0
T12	0	201	0	0
T13	0	35	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25214374	1068	0	0
T1	5696	2	0	0
T2	61469	0	0	0
T3	11667	0	0	0
T4	2477	0	0	0
T5	10042	0	0	0
T6	6991	0	0	0
T7	16439	7	0	0
T8	91160	0	0	0
T9	9275	0	0	0
T10	243248	18	0	0
T12	0	27	0	0
T23	0	6	0	0
T35	0	33	0	0
T36	0	21	0	0
T50	0	5	0	0
T51	0	20	0	0
T105	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25214374	12696	0	0
T1	5696	2	0	0
T2	61469	24	0	0
T3	11667	0	0	0
T4	2477	0	0	0
T5	10042	0	0	0
T6	6991	4	0	0
T7	16439	15	0	0
T8	91160	68	0	0
T9	9275	12	0	0
T10	243248	222	0	0
T11	0	10	0	0
T12	0	201	0	0
T13	0	35	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25214374	1068	0	0
T1	5696	2	0	0
T2	61469	0	0	0
T3	11667	0	0	0
T4	2477	0	0	0
T5	10042	0	0	0
T6	6991	0	0	0
T7	16439	7	0	0
T8	91160	0	0	0
T9	9275	0	0	0
T10	243248	18	0	0
T12	0	27	0	0
T23	0	6	0	0
T35	0	33	0	0
T36	0	21	0	0
T50	0	5	0	0
T51	0	20	0	0
T105	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25214129	12785	0	0
T1	5696	3	0	0
T2	61459	24	0	0
T3	11673	0	0	0
T4	2477	0	0	0
T5	10041	0	0	0
T6	6991	4	0	0
T7	16434	14	0	0
T8	91139	68	0	0
T9	9275	12	0	0
T10	243218	218	0	0
T11	0	10	0	0
T12	0	199	0	0
T13	0	35	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25214129	1152	0	0
T1	5696	3	0	0
T2	61459	0	0	0
T3	11673	0	0	0
T4	2477	0	0	0
T5	10041	0	0	0
T6	6991	0	0	0
T7	16434	6	0	0
T8	91139	0	0	0
T9	9275	0	0	0
T10	243218	14	0	0
T12	0	25	0	0
T23	0	7	0	0
T35	0	29	0	0
T36	0	25	0	0
T50	0	6	0	0
T51	0	22	0	0
T106	0	13	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25214129	12785	0	0
T1	5696	3	0	0
T2	61459	24	0	0
T3	11673	0	0	0
T4	2477	0	0	0
T5	10041	0	0	0
T6	6991	4	0	0
T7	16434	14	0	0
T8	91139	68	0	0
T9	9275	12	0	0
T10	243218	218	0	0
T11	0	10	0	0
T12	0	199	0	0
T13	0	35	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25214129	1152	0	0
T1	5696	3	0	0
T2	61459	0	0	0
T3	11673	0	0	0
T4	2477	0	0	0
T5	10041	0	0	0
T6	6991	0	0	0
T7	16434	6	0	0
T8	91139	0	0	0
T9	9275	0	0	0
T10	243218	14	0	0
T12	0	25	0	0
T23	0	7	0	0
T35	0	29	0	0
T36	0	25	0	0
T50	0	6	0	0
T51	0	22	0	0
T106	0	13	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593342	21814	0	0
T1	354	5	0	0
T2	3927	47	0	0
T3	731	3	0	0
T4	154	1	0	0
T5	627	2	0	0
T6	436	6	0	0
T7	1027	19	0	0
T8	5712	91	0	0
T9	579	14	0	0
T10	15708	334	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593342	1187	0	0
T1	354	4	0	0
T2	3927	0	0	0
T3	731	0	0	0
T4	154	0	0	0
T5	627	0	0	0
T6	436	0	0	0
T7	1027	7	0	0
T8	5712	0	0	0
T9	579	0	0	0
T10	15708	18	0	0
T12	0	31	0	0
T23	0	10	0	0
T35	0	34	0	0
T36	0	24	0	0
T50	0	7	0	0
T51	0	22	0	0
T106	0	16	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593342	21814	0	0
T1	354	5	0	0
T2	3927	47	0	0
T3	731	3	0	0
T4	154	1	0	0
T5	627	2	0	0
T6	436	6	0	0
T7	1027	19	0	0
T8	5712	91	0	0
T9	579	14	0	0
T10	15708	334	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593342	1187	0	0
T1	354	4	0	0
T2	3927	0	0	0
T3	731	0	0	0
T4	154	0	0	0
T5	627	0	0	0
T6	436	0	0	0
T7	1027	7	0	0
T8	5712	0	0	0
T9	579	0	0	0
T10	15708	18	0	0
T12	0	31	0	0
T23	0	10	0	0
T35	0	34	0	0
T36	0	24	0	0
T50	0	7	0	0
T51	0	22	0	0
T106	0	16	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	14122	0	0
T1	2847	5	0	0
T2	30735	29	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	4	0	0
T7	8219	16	0	0
T8	45579	75	0	0
T9	4638	14	0	0
T10	121628	240	0	0
T11	0	12	0	0
T12	0	213	0	0
T13	0	36	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	1210	0	0
T1	2847	5	0	0
T2	30735	0	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	0	0	0
T7	8219	8	0	0
T8	45579	0	0	0
T9	4638	0	0	0
T10	121628	20	0	0
T12	0	28	0	0
T23	0	11	0	0
T35	0	28	0	0
T36	0	19	0	0
T50	0	8	0	0
T51	0	17	0	0
T106	0	15	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	14122	0	0
T1	2847	5	0	0
T2	30735	29	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	4	0	0
T7	8219	16	0	0
T8	45579	75	0	0
T9	4638	14	0	0
T10	121628	240	0	0
T11	0	12	0	0
T12	0	213	0	0
T13	0	36	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	1210	0	0
T1	2847	5	0	0
T2	30735	0	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	0	0	0
T7	8219	8	0	0
T8	45579	0	0	0
T9	4638	0	0	0
T10	121628	20	0	0
T12	0	28	0	0
T23	0	11	0	0
T35	0	28	0	0
T36	0	19	0	0
T50	0	8	0	0
T51	0	17	0	0
T106	0	15	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	14184	0	0
T1	2847	6	0	0
T2	30735	29	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	4	0	0
T7	8219	16	0	0
T8	45579	75	0	0
T9	4638	14	0	0
T10	121628	238	0	0
T11	0	12	0	0
T12	0	215	0	0
T13	0	36	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	1278	0	0
T1	2847	6	0	0
T2	30735	0	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	0	0	0
T7	8219	9	0	0
T8	45579	0	0	0
T9	4638	0	0	0
T10	121628	18	0	0
T12	0	28	0	0
T23	0	10	0	0
T35	0	32	0	0
T36	0	25	0	0
T50	0	8	0	0
T51	0	24	0	0
T106	0	17	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	14184	0	0
T1	2847	6	0	0
T2	30735	29	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	4	0	0
T7	8219	16	0	0
T8	45579	75	0	0
T9	4638	14	0	0
T10	121628	238	0	0
T11	0	12	0	0
T12	0	215	0	0
T13	0	36	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	1278	0	0
T1	2847	6	0	0
T2	30735	0	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	0	0	0
T7	8219	9	0	0
T8	45579	0	0	0
T9	4638	0	0	0
T10	121628	18	0	0
T12	0	28	0	0
T23	0	10	0	0
T35	0	32	0	0
T36	0	25	0	0
T50	0	8	0	0
T51	0	24	0	0
T106	0	17	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	14248	0	0
T1	2847	7	0	0
T2	30735	29	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	4	0	0
T7	8219	16	0	0
T8	45579	75	0	0
T9	4638	14	0	0
T10	121628	238	0	0
T11	0	12	0	0
T12	0	213	0	0
T13	0	36	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	1331	0	0
T1	2847	7	0	0
T2	30735	0	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	0	0	0
T7	8219	8	0	0
T8	45579	0	0	0
T9	4638	0	0	0
T10	121628	19	0	0
T12	0	26	0	0
T23	0	12	0	0
T35	0	29	0	0
T36	0	25	0	0
T50	0	8	0	0
T51	0	19	0	0
T105	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	14248	0	0
T1	2847	7	0	0
T2	30735	29	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	4	0	0
T7	8219	16	0	0
T8	45579	75	0	0
T9	4638	14	0	0
T10	121628	238	0	0
T11	0	12	0	0
T12	0	213	0	0
T13	0	36	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	1331	0	0
T1	2847	7	0	0
T2	30735	0	0	0
T3	5830	0	0	0
T4	1238	0	0	0
T5	5020	0	0	0
T6	3496	0	0	0
T7	8219	8	0	0
T8	45579	0	0	0
T9	4638	0	0	0
T10	121628	19	0	0
T12	0	26	0	0
T23	0	12	0	0
T35	0	29	0	0
T36	0	25	0	0
T50	0	8	0	0
T51	0	19	0	0
T105	0	1	0	0