Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11895605	7614	0	0
alert_regwen_rd_A	11895605	4673	0	0
cpu_regwen_rd_A	11895605	4920	0	0
sw_rst_ctrl_n_0_rd_A	11895605	9496	0	0
sw_rst_ctrl_n_1_rd_A	11895605	9547	0	0
sw_rst_ctrl_n_2_rd_A	11895605	9302	0	0
sw_rst_ctrl_n_3_rd_A	11895605	9291	0	0
sw_rst_ctrl_n_4_rd_A	11895605	9596	0	0
sw_rst_ctrl_n_5_rd_A	11895605	9446	0	0
sw_rst_ctrl_n_6_rd_A	11895605	9527	0	0
sw_rst_ctrl_n_7_rd_A	11895605	9078	0	0
sw_rst_regwen_0_rd_A	11895605	5259	0	0
sw_rst_regwen_1_rd_A	11895605	5323	0	0
sw_rst_regwen_2_rd_A	11895605	5154	0	0
sw_rst_regwen_3_rd_A	11895605	4999	0	0
sw_rst_regwen_4_rd_A	11895605	5315	0	0
sw_rst_regwen_5_rd_A	11895605	5388	0	0
sw_rst_regwen_6_rd_A	11895605	5235	0	0
sw_rst_regwen_7_rd_A	11895605	5133	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	7614	0	0
T65	4126	180	0	0
T66	11040	2	0	0
T67	9222	1	0	0
T68	10039	454	0	0
T69	16916	3	0	0
T70	3677	45	0	0
T71	19669	2	0	0
T87	7132	217	0	0
T88	5318	239	0	0
T91	6345	225	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	4673	0	0
T12	237574	330	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	45	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	83	0	0
T126	0	54	0	0
T127	0	56	0	0
T128	0	294	0	0
T129	0	42	0	0
T130	0	69	0	0
T131	0	55	0	0
T132	0	187	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	4920	0	0
T12	237574	372	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	76	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	104	0	0
T126	0	57	0	0
T127	0	71	0	0
T128	0	331	0	0
T129	0	27	0	0
T130	0	65	0	0
T131	0	72	0	0
T132	0	235	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	9496	0	0
T12	237574	743	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	65	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	96	0	0
T126	0	73	0	0
T133	0	26	0	0
T134	0	19	0	0
T135	0	212	0	0
T136	0	21	0	0
T137	0	13	0	0
T138	0	18	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	9547	0	0
T12	237574	707	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	60	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	103	0	0
T126	0	43	0	0
T133	0	28	0	0
T134	0	11	0	0
T135	0	237	0	0
T136	0	8	0	0
T137	0	22	0	0
T138	0	20	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	9302	0	0
T12	237574	723	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	37	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	110	0	0
T126	0	51	0	0
T133	0	26	0	0
T134	0	13	0	0
T135	0	231	0	0
T136	0	17	0	0
T137	0	15	0	0
T138	0	14	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	9291	0	0
T12	237574	766	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	63	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	92	0	0
T126	0	43	0	0
T133	0	33	0	0
T134	0	10	0	0
T135	0	212	0	0
T136	0	22	0	0
T137	0	22	0	0
T138	0	13	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	9596	0	0
T12	237574	707	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	60	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	90	0	0
T126	0	55	0	0
T133	0	29	0	0
T134	0	19	0	0
T135	0	201	0	0
T136	0	4	0	0
T137	0	17	0	0
T138	0	19	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	9446	0	0
T12	237574	690	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	49	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	98	0	0
T126	0	73	0	0
T133	0	30	0	0
T134	0	11	0	0
T135	0	243	0	0
T136	0	10	0	0
T137	0	23	0	0
T138	0	26	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	9527	0	0
T12	237574	651	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	73	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	87	0	0
T126	0	56	0	0
T133	0	24	0	0
T134	0	15	0	0
T135	0	236	0	0
T136	0	24	0	0
T137	0	18	0	0
T138	0	10	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	9078	0	0
T12	237574	752	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	55	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	109	0	0
T126	0	51	0	0
T133	0	29	0	0
T134	0	17	0	0
T135	0	249	0	0
T136	0	20	0	0
T137	0	11	0	0
T138	0	8	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	5259	0	0
T12	237574	349	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	52	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	96	0	0
T126	0	45	0	0
T134	0	8	0	0
T135	0	45	0	0
T136	0	8	0	0
T138	0	10	0	0
T139	0	23	0	0
T140	0	4	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	5323	0	0
T12	237574	426	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	75	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	94	0	0
T126	0	44	0	0
T134	0	9	0	0
T135	0	30	0	0
T136	0	1	0	0
T138	0	8	0	0
T139	0	32	0	0
T140	0	4	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	5154	0	0
T12	237574	326	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	66	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	103	0	0
T126	0	46	0	0
T134	0	6	0	0
T135	0	30	0	0
T136	0	6	0	0
T139	0	7	0	0
T140	0	10	0	0
T141	0	6	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	4999	0	0
T12	237574	342	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	54	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	86	0	0
T126	0	51	0	0
T134	0	10	0	0
T135	0	44	0	0
T136	0	6	0	0
T138	0	9	0	0
T139	0	13	0	0
T141	0	5	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	5315	0	0
T12	237574	398	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	86	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	108	0	0
T126	0	41	0	0
T134	0	12	0	0
T135	0	43	0	0
T136	0	12	0	0
T138	0	7	0	0
T139	0	23	0	0
T141	0	3	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	5388	0	0
T12	237574	332	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	46	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	106	0	0
T126	0	32	0	0
T134	0	5	0	0
T135	0	35	0	0
T136	0	4	0	0
T138	0	9	0	0
T139	0	15	0	0
T141	0	1	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	5235	0	0
T12	237574	359	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	55	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	113	0	0
T126	0	64	0	0
T134	0	6	0	0
T135	0	25	0	0
T136	0	8	0	0
T138	0	13	0	0
T139	0	18	0	0
T141	0	12	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11895605	5133	0	0
T12	237574	301	0	0
T13	33828	0	0	0
T14	2585	0	0	0
T23	7818	0	0	0
T24	4683	0	0	0
T41	0	56	0	0
T49	17986	0	0	0
T50	6609	0	0	0
T51	100822	0	0	0
T103	13251	0	0	0
T108	17559	0	0	0
T113	0	124	0	0
T126	0	43	0	0
T134	0	1	0	0
T135	0	36	0	0
T136	0	3	0	0
T138	0	4	0	0
T139	0	11	0	0
T141	0	2	0	0