Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T10,T12

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T6,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52529170	9018	0	0
CascadeEffAonToRstPorAboveRise_A	52529170	9018	0	0
CascadeEffAonToRstPorIoAboveFall_A	50426463	9018	0	0
CascadeEffAonToRstPorIoAboveRise_A	50426463	9018	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25214374	9018	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25214374	9018	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12606835	9018	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12606835	9018	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25214129	9018	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25214129	9018	0	0
CascadeLcToLcAboveFall_A	52529170	21970	0	0
CascadeLcToLcAboveRise_A	52529170	21970	0	0
CascadeLcToLcAonAboveFall_A	1593342	21970	0	0
CascadeLcToLcAonAboveRise_A	1593342	21970	0	0
CascadeLcToLcShadowedAboveFall_A	52529170	21970	0	0
CascadeLcToLcShadowedAboveRise_A	52529170	21970	0	0
CascadePorToAonAboveFall_A	1593342	7280	0	0
CascadeSysToSysAboveFall_A	52529170	21970	0	0
CascadeSysToSysAboveRise_A	52529170	21970	0	0
ScanRstToAonRise_A	1593342	240	0	0
StablePorToAonRise_A	1593342	9018	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11162868	21970	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11162868	21970	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11162868	21970	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11162868	21970	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12606835	21970	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12606835	21970	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11162868	21970	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11162868	21970	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11162868	21970	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11162868	21970	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52529170	9018	0	0
T1	11868	1	0	0
T2	128079	18	0	0
T3	24300	8	0	0
T4	5161	1	0	0
T5	20919	2	0	0
T6	14568	2	0	0
T7	34238	5	0	0
T8	189873	27	0	0
T9	19326	1	0	0
T10	506732	101	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52529170	9018	0	0
T1	11868	1	0	0
T2	128079	18	0	0
T3	24300	8	0	0
T4	5161	1	0	0
T5	20919	2	0	0
T6	14568	2	0	0
T7	34238	5	0	0
T8	189873	27	0	0
T9	19326	1	0	0
T10	506732	101	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50426463	9018	0	0
T1	11395	1	0	0
T2	122928	18	0	0
T3	23322	8	0	0
T4	4954	1	0	0
T5	20083	2	0	0
T6	13980	2	0	0
T7	32867	5	0	0
T8	182287	27	0	0
T9	18551	1	0	0
T10	486426	101	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50426463	9018	0	0
T1	11395	1	0	0
T2	122928	18	0	0
T3	23322	8	0	0
T4	4954	1	0	0
T5	20083	2	0	0
T6	13980	2	0	0
T7	32867	5	0	0
T8	182287	27	0	0
T9	18551	1	0	0
T10	486426	101	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25214374	9018	0	0
T1	5696	1	0	0
T2	61469	18	0	0
T3	11667	8	0	0
T4	2477	1	0	0
T5	10042	2	0	0
T6	6991	2	0	0
T7	16439	5	0	0
T8	91160	27	0	0
T9	9275	1	0	0
T10	243248	101	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25214374	9018	0	0
T1	5696	1	0	0
T2	61469	18	0	0
T3	11667	8	0	0
T4	2477	1	0	0
T5	10042	2	0	0
T6	6991	2	0	0
T7	16439	5	0	0
T8	91160	27	0	0
T9	9275	1	0	0
T10	243248	101	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	9018	0	0
T1	2847	1	0	0
T2	30735	18	0	0
T3	5830	8	0	0
T4	1238	1	0	0
T5	5020	2	0	0
T6	3496	2	0	0
T7	8219	5	0	0
T8	45579	27	0	0
T9	4638	1	0	0
T10	121628	101	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	9018	0	0
T1	2847	1	0	0
T2	30735	18	0	0
T3	5830	8	0	0
T4	1238	1	0	0
T5	5020	2	0	0
T6	3496	2	0	0
T7	8219	5	0	0
T8	45579	27	0	0
T9	4638	1	0	0
T10	121628	101	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25214129	9018	0	0
T1	5696	1	0	0
T2	61459	18	0	0
T3	11673	8	0	0
T4	2477	1	0	0
T5	10041	2	0	0
T6	6991	2	0	0
T7	16434	5	0	0
T8	91139	27	0	0
T9	9275	1	0	0
T10	243218	101	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25214129	9018	0	0
T1	5696	1	0	0
T2	61459	18	0	0
T3	11673	8	0	0
T4	2477	1	0	0
T5	10041	2	0	0
T6	6991	2	0	0
T7	16434	5	0	0
T8	91139	27	0	0
T9	9275	1	0	0
T10	243218	101	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52529170	21970	0	0
T1	11868	1	0	0
T2	128079	47	0	0
T3	24300	8	0	0
T4	5161	1	0	0
T5	20919	2	0	0
T6	14568	6	0	0
T7	34238	13	0	0
T8	189873	102	0	0
T9	19326	15	0	0
T10	506732	321	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52529170	21970	0	0
T1	11868	1	0	0
T2	128079	47	0	0
T3	24300	8	0	0
T4	5161	1	0	0
T5	20919	2	0	0
T6	14568	6	0	0
T7	34238	13	0	0
T8	189873	102	0	0
T9	19326	15	0	0
T10	506732	321	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593342	21970	0	0
T1	354	1	0	0
T2	3927	47	0	0
T3	731	8	0	0
T4	154	1	0	0
T5	627	2	0	0
T6	436	6	0	0
T7	1027	13	0	0
T8	5712	102	0	0
T9	579	15	0	0
T10	15708	321	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593342	21970	0	0
T1	354	1	0	0
T2	3927	47	0	0
T3	731	8	0	0
T4	154	1	0	0
T5	627	2	0	0
T6	436	6	0	0
T7	1027	13	0	0
T8	5712	102	0	0
T9	579	15	0	0
T10	15708	321	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52529170	21970	0	0
T1	11868	1	0	0
T2	128079	47	0	0
T3	24300	8	0	0
T4	5161	1	0	0
T5	20919	2	0	0
T6	14568	6	0	0
T7	34238	13	0	0
T8	189873	102	0	0
T9	19326	15	0	0
T10	506732	321	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52529170	21970	0	0
T1	11868	1	0	0
T2	128079	47	0	0
T3	24300	8	0	0
T4	5161	1	0	0
T5	20919	2	0	0
T6	14568	6	0	0
T7	34238	13	0	0
T8	189873	102	0	0
T9	19326	15	0	0
T10	506732	321	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593342	7280	0	0
T1	354	1	0	0
T2	3927	11	0	0
T3	731	8	0	0
T4	154	1	0	0
T5	627	20	0	0
T6	436	1	0	0
T7	1027	3	0	0
T8	5712	27	0	0
T9	579	1	0	0
T10	15708	46	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52529170	21970	0	0
T1	11868	1	0	0
T2	128079	47	0	0
T3	24300	8	0	0
T4	5161	1	0	0
T5	20919	2	0	0
T6	14568	6	0	0
T7	34238	13	0	0
T8	189873	102	0	0
T9	19326	15	0	0
T10	506732	321	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52529170	21970	0	0
T1	11868	1	0	0
T2	128079	47	0	0
T3	24300	8	0	0
T4	5161	1	0	0
T5	20919	2	0	0
T6	14568	6	0	0
T7	34238	13	0	0
T8	189873	102	0	0
T9	19326	15	0	0
T10	506732	321	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593342	240	0	0
T10	15708	5	0	0
T11	385	0	0	0
T12	33225	4	0	0
T13	5037	0	0	0
T23	978	0	0	0
T24	620	0	0	0
T35	0	4	0	0
T36	0	4	0	0
T41	0	1	0	0
T49	3023	4	0	0
T50	832	0	0	0
T51	16630	4	0	0
T103	2270	0	0	0
T106	0	5	0	0
T115	0	3	0	0
T142	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593342	9018	0	0
T1	354	1	0	0
T2	3927	18	0	0
T3	731	8	0	0
T4	154	1	0	0
T5	627	2	0	0
T6	436	2	0	0
T7	1027	5	0	0
T8	5712	27	0	0
T9	579	1	0	0
T10	15708	101	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11162868	21970	0	0
T1	2757	1	0	0
T2	27110	47	0	0
T3	5095	8	0	0
T4	1219	1	0	0
T5	4929	2	0	0
T6	3352	6	0	0
T7	7470	13	0	0
T8	42475	102	0	0
T9	3585	15	0	0
T10	96366	321	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11162868	21970	0	0
T1	2757	1	0	0
T2	27110	47	0	0
T3	5095	8	0	0
T4	1219	1	0	0
T5	4929	2	0	0
T6	3352	6	0	0
T7	7470	13	0	0
T8	42475	102	0	0
T9	3585	15	0	0
T10	96366	321	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11162868	21970	0	0
T1	2757	1	0	0
T2	27110	47	0	0
T3	5095	8	0	0
T4	1219	1	0	0
T5	4929	2	0	0
T6	3352	6	0	0
T7	7470	13	0	0
T8	42475	102	0	0
T9	3585	15	0	0
T10	96366	321	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11162868	21970	0	0
T1	2757	1	0	0
T2	27110	47	0	0
T3	5095	8	0	0
T4	1219	1	0	0
T5	4929	2	0	0
T6	3352	6	0	0
T7	7470	13	0	0
T8	42475	102	0	0
T9	3585	15	0	0
T10	96366	321	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	21970	0	0
T1	2847	1	0	0
T2	30735	47	0	0
T3	5830	8	0	0
T4	1238	1	0	0
T5	5020	2	0	0
T6	3496	6	0	0
T7	8219	13	0	0
T8	45579	102	0	0
T9	4638	15	0	0
T10	121628	321	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606835	21970	0	0
T1	2847	1	0	0
T2	30735	47	0	0
T3	5830	8	0	0
T4	1238	1	0	0
T5	5020	2	0	0
T6	3496	6	0	0
T7	8219	13	0	0
T8	45579	102	0	0
T9	4638	15	0	0
T10	121628	321	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11162868	21970	0	0
T1	2757	1	0	0
T2	27110	47	0	0
T3	5095	8	0	0
T4	1219	1	0	0
T5	4929	2	0	0
T6	3352	6	0	0
T7	7470	13	0	0
T8	42475	102	0	0
T9	3585	15	0	0
T10	96366	321	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11162868	21970	0	0
T1	2757	1	0	0
T2	27110	47	0	0
T3	5095	8	0	0
T4	1219	1	0	0
T5	4929	2	0	0
T6	3352	6	0	0
T7	7470	13	0	0
T8	42475	102	0	0
T9	3585	15	0	0
T10	96366	321	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11162868	21970	0	0
T1	2757	1	0	0
T2	27110	47	0	0
T3	5095	8	0	0
T4	1219	1	0	0
T5	4929	2	0	0
T6	3352	6	0	0
T7	7470	13	0	0
T8	42475	102	0	0
T9	3585	15	0	0
T10	96366	321	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11162868	21970	0	0
T1	2757	1	0	0
T2	27110	47	0	0
T3	5095	8	0	0
T4	1219	1	0	0
T5	4929	2	0	0
T6	3352	6	0	0
T7	7470	13	0	0
T8	42475	102	0	0
T9	3585	15	0	0
T10	96366	321	0	0