Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	610730	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

365819

1

T1

1048

T2

256

T3

138

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	519608	1			T1	1500		T2	395		T3	186
values[0x0]	227827	1			T1	841		T2	166		T3	97
values[0x1]	229114	1			T1	859		T2	183		T3	96

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	512450	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

464099

1

T1

1422

T2

328

T3

167

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3247	1			T1	1		T4	3		T7	36
valid_sources[0x01]	4053	1			T1	9		T4	6		T6	2
valid_sources[0x02]	3648	1			T1	8		T4	1		T7	1
valid_sources[0x03]	3142	1			T1	8		T4	1		T7	5
valid_sources[0x04]	2941	1			T1	16		T4	4		T7	17
valid_sources[0x05]	3556	1			T1	10		T4	5		T24	34
valid_sources[0x06]	3818	1			T1	20		T4	3		T24	44
valid_sources[0x07]	3074	1			T1	6		T4	1		T7	30
valid_sources[0x08]	3209	1			T1	25		T4	2		T24	32
valid_sources[0x09]	3292	1			T1	14		T4	3		T7	10
valid_sources[0x0a]	4881	1			T1	15		T4	2		T7	41
valid_sources[0x0b]	3212	1			T1	16		T4	8		T7	2
valid_sources[0x0c]	6848	1			T1	9		T4	8		T7	15
valid_sources[0x0d]	3671	1			T1	5		T4	2		T7	18
valid_sources[0x0e]	3289	1			T1	29		T4	2		T7	23
valid_sources[0x0f]	3903	1			T1	6		T4	1		T7	34
valid_sources[0x10]	3412	1			T1	3		T4	1		T7	21
valid_sources[0x11]	4124	1			T1	9		T4	8		T24	29
valid_sources[0x12]	3481	1			T1	9		T24	25		T35	198
valid_sources[0x13]	3286	1			T1	13		T4	1		T7	2
valid_sources[0x14]	4220	1			T1	4		T4	3		T7	10
valid_sources[0x15]	3481	1			T1	21		T7	4		T11	4
valid_sources[0x16]	3952	1			T1	4		T4	10		T6	325
valid_sources[0x17]	4270	1			T1	10		T4	1		T7	39
valid_sources[0x18]	3348	1			T1	20		T4	12		T7	7
valid_sources[0x19]	3889	1			T1	11		T4	1		T7	34
valid_sources[0x1a]	3202	1			T1	14		T4	2		T7	15
valid_sources[0x1b]	4365	1			T1	13		T4	4		T7	94
valid_sources[0x1c]	3982	1			T1	11		T4	1		T6	2
valid_sources[0x1d]	3332	1			T1	12		T4	5		T7	1
valid_sources[0x1e]	3289	1			T1	11		T4	5		T24	21
valid_sources[0x1f]	3361	1			T1	13		T4	3		T7	20
valid_sources[0x20]	3366	1			T1	16		T4	14		T7	10
valid_sources[0x21]	3701	1			T1	19		T4	1		T7	23
valid_sources[0x22]	3242	1			T1	4		T4	2		T7	24
valid_sources[0x23]	3099	1			T1	7		T4	3		T7	2
valid_sources[0x24]	3367	1			T1	11		T4	2		T11	1
valid_sources[0x25]	3545	1			T1	7		T4	5		T6	425
valid_sources[0x26]	3411	1			T1	13		T4	3		T6	62
valid_sources[0x27]	3146	1			T1	12		T4	2		T24	33
valid_sources[0x28]	3055	1			T1	7		T4	5		T24	32
valid_sources[0x29]	3405	1			T1	13		T4	2		T7	47
valid_sources[0x2a]	3958	1			T1	13		T4	2		T7	49
valid_sources[0x2b]	3455	1			T1	8		T4	1		T7	4
valid_sources[0x2c]	3757	1			T1	12		T4	1		T7	14
valid_sources[0x2d]	3971	1			T1	14		T7	8		T24	42
valid_sources[0x2e]	3841	1			T1	11		T4	1		T7	59
valid_sources[0x2f]	3549	1			T1	11		T4	3		T7	5
valid_sources[0x30]	4457	1			T1	13		T2	744		T4	2
valid_sources[0x31]	3956	1			T1	5		T4	1		T24	21
valid_sources[0x32]	2789	1			T1	10		T7	8		T11	2
valid_sources[0x33]	3312	1			T1	10		T7	10		T24	27
valid_sources[0x34]	3820	1			T1	19		T4	1		T24	26
valid_sources[0x35]	3010	1			T1	13		T4	1		T7	50
valid_sources[0x36]	3496	1			T1	17		T4	4		T7	8
valid_sources[0x37]	5295	1			T1	16		T4	6		T7	3
valid_sources[0x38]	5652	1			T1	12		T4	1		T7	7
valid_sources[0x39]	3463	1			T1	18		T4	1		T7	60
valid_sources[0x3a]	3189	1			T1	15		T4	2		T7	4
valid_sources[0x3b]	5403	1			T1	21		T4	8		T7	3
valid_sources[0x3c]	3968	1			T1	3		T4	2		T7	1
valid_sources[0x3d]	3326	1			T1	11		T4	5		T7	6
valid_sources[0x3e]	2858	1			T1	21		T4	1		T7	18
valid_sources[0x3f]	3851	1			T1	19		T7	5		T24	27
valid_sources[0x40]	3242	1			T1	5		T4	1		T12	6
valid_sources[0x41]	3284	1			T1	11		T4	9		T7	1
valid_sources[0x42]	3505	1			T1	9		T4	7		T6	112
valid_sources[0x43]	3277	1			T1	23		T4	4		T7	16
valid_sources[0x44]	4194	1			T1	11		T4	3		T7	18
valid_sources[0x45]	6645	1			T1	10		T4	9		T24	32
valid_sources[0x46]	3408	1			T1	16		T4	5		T24	30
valid_sources[0x47]	4557	1			T1	7		T4	2		T6	5
valid_sources[0x48]	3476	1			T1	25		T4	6		T7	9
valid_sources[0x49]	4278	1			T1	11		T4	2		T7	5
valid_sources[0x4a]	3111	1			T1	10		T4	4		T11	3
valid_sources[0x4b]	3473	1			T1	7		T4	9		T7	19
valid_sources[0x4c]	2986	1			T1	4		T4	2		T7	20
valid_sources[0x4d]	3084	1			T1	8		T4	5		T7	4
valid_sources[0x4e]	3960	1			T1	5		T4	1		T7	44
valid_sources[0x4f]	3239	1			T1	10		T6	13		T7	19
valid_sources[0x50]	3309	1			T1	15		T4	1		T24	35
valid_sources[0x51]	4143	1			T1	19		T4	4		T7	1
valid_sources[0x52]	3576	1			T1	18		T4	2		T11	2
valid_sources[0x53]	3444	1			T1	12		T4	1		T24	40
valid_sources[0x54]	4291	1			T1	10		T4	5		T24	32
valid_sources[0x55]	3429	1			T1	20		T4	10		T24	17
valid_sources[0x56]	3068	1			T1	15		T4	7		T7	6
valid_sources[0x57]	3697	1			T1	20		T7	6		T11	1
valid_sources[0x58]	4253	1			T1	8		T6	3		T7	41
valid_sources[0x59]	3789	1			T1	9		T24	33		T42	9
valid_sources[0x5a]	3814	1			T1	9		T4	3		T6	278
valid_sources[0x5b]	3358	1			T1	15		T4	5		T7	1
valid_sources[0x5c]	3730	1			T1	6		T4	1		T7	27
valid_sources[0x5d]	3596	1			T1	12		T4	11		T7	1
valid_sources[0x5e]	2860	1			T1	18		T4	9		T7	12
valid_sources[0x5f]	3507	1			T1	15		T4	5		T7	23
valid_sources[0x60]	3795	1			T1	12		T4	1		T7	3
valid_sources[0x61]	3354	1			T1	25		T4	5		T7	4
valid_sources[0x62]	4689	1			T1	3		T4	5		T24	28
valid_sources[0x63]	3275	1			T1	13		T4	3		T6	7
valid_sources[0x64]	3937	1			T1	11		T7	33		T24	30
valid_sources[0x65]	3896	1			T1	20		T7	6		T24	28
valid_sources[0x66]	3696	1			T1	18		T4	10		T24	30
valid_sources[0x67]	3023	1			T1	17		T4	2		T7	12
valid_sources[0x68]	3692	1			T1	5		T4	4		T24	30
valid_sources[0x69]	4675	1			T1	10		T3	379		T7	43
valid_sources[0x6a]	4132	1			T1	11		T4	2		T7	2
valid_sources[0x6b]	5937	1			T1	13		T4	5		T7	34
valid_sources[0x6c]	3738	1			T1	7		T4	12		T7	15
valid_sources[0x6d]	5322	1			T1	7		T24	38		T25	1
valid_sources[0x6e]	3547	1			T1	9		T4	6		T14	5
valid_sources[0x6f]	3591	1			T1	15		T4	1		T6	70
valid_sources[0x70]	3197	1			T1	14		T4	11		T7	25
valid_sources[0x71]	3807	1			T1	21		T4	4		T7	10
valid_sources[0x72]	3220	1			T1	16		T4	6		T7	13
valid_sources[0x73]	4078	1			T1	4		T7	1		T24	42
valid_sources[0x74]	3690	1			T1	11		T4	5		T7	4
valid_sources[0x75]	3849	1			T1	7		T4	4		T6	273
valid_sources[0x76]	4267	1			T1	14		T7	4		T24	24
valid_sources[0x77]	6445	1			T1	16		T4	5		T24	28
valid_sources[0x78]	3584	1			T1	8		T4	5		T7	24
valid_sources[0x79]	3676	1			T1	12		T7	4		T14	9
valid_sources[0x7a]	3212	1			T1	8		T4	5		T11	1
valid_sources[0x7b]	3876	1			T1	8		T4	4		T7	16
valid_sources[0x7c]	4212	1			T1	15		T4	2		T7	45
valid_sources[0x7d]	3759	1			T1	15		T4	3		T24	27
valid_sources[0x7e]	3272	1			T1	19		T4	1		T7	15
valid_sources[0x7f]	3786	1			T1	8		T4	3		T7	9
valid_sources[0x80]	3051	1			T1	14		T4	1		T24	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

243850

1

T1

644

T2

195

T3

82

values[0x0]

all_enables

biggest_size

79384

1

T1

277

T2

37

T3

34

values[0x1]

all_enables

biggest_size

42585

1

T1

127

T2

24

T3

22