Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T11
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T24
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T24
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T24
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T24
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T24
1	0	Covered	T1,T3,T5

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12619161	13924	0	0
gen_assertions[0].RstEnOn_A	12619161	1033	0	0
gen_assertions[0].RstNOff_A	12619161	13924	0	0
gen_assertions[0].RstNOn_A	12619161	1033	0	0
gen_assertions[1].RstEnOff_A	50475698	12619	0	0
gen_assertions[1].RstEnOn_A	50475698	1006	0	0
gen_assertions[1].RstNOff_A	50475698	12619	0	0
gen_assertions[1].RstNOn_A	50475698	1006	0	0
gen_assertions[2].RstEnOff_A	25238720	12678	0	0
gen_assertions[2].RstEnOn_A	25238720	1019	0	0
gen_assertions[2].RstNOff_A	25238720	12678	0	0
gen_assertions[2].RstNOn_A	25238720	1019	0	0
gen_assertions[3].RstEnOff_A	25238705	12723	0	0
gen_assertions[3].RstEnOn_A	25238705	1069	0	0
gen_assertions[3].RstNOff_A	25238705	12723	0	0
gen_assertions[3].RstNOn_A	25238705	1069	0	0
gen_assertions[4].RstEnOff_A	1593360	21302	0	0
gen_assertions[4].RstEnOn_A	1593360	1122	0	0
gen_assertions[4].RstNOff_A	1593360	21302	0	0
gen_assertions[4].RstNOn_A	1593360	1122	0	0
gen_assertions[5].RstEnOff_A	12619161	14197	0	0
gen_assertions[5].RstEnOn_A	12619161	1176	0	0
gen_assertions[5].RstNOff_A	12619161	14197	0	0
gen_assertions[5].RstNOn_A	12619161	1176	0	0
gen_assertions[6].RstEnOff_A	12619161	14247	0	0
gen_assertions[6].RstEnOn_A	12619161	1230	0	0
gen_assertions[6].RstNOff_A	12619161	14247	0	0
gen_assertions[6].RstNOn_A	12619161	1230	0	0
gen_assertions[7].RstEnOff_A	12619161	14285	0	0
gen_assertions[7].RstEnOn_A	12619161	1268	0	0
gen_assertions[7].RstNOff_A	12619161	14285	0	0
gen_assertions[7].RstNOn_A	12619161	1268	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	13924	0	0
T1	56177	75	0	0
T2	8102	1	0	0
T3	5616	4	0	0
T4	10377	4	0	0
T5	2710	0	0	0
T6	34975	29	0	0
T7	29284	75	0	0
T8	5842	0	0	0
T9	56308	75	0	0
T10	1451	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T14	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	1033	0	0
T2	8102	1	0	0
T3	5616	0	0	0
T4	10377	4	0	0
T5	2710	0	0	0
T6	34975	0	0	0
T7	29284	0	0	0
T8	5842	0	0	0
T9	56308	0	0	0
T10	1451	0	0	0
T11	3037	0	0	0
T24	0	36	0	0
T53	0	8	0	0
T60	0	1	0	0
T78	0	5	0	0
T79	0	6	0	0
T80	0	3	0	0
T81	0	7	0	0
T82	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	13924	0	0
T1	56177	75	0	0
T2	8102	1	0	0
T3	5616	4	0	0
T4	10377	4	0	0
T5	2710	0	0	0
T6	34975	29	0	0
T7	29284	75	0	0
T8	5842	0	0	0
T9	56308	75	0	0
T10	1451	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T14	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	1033	0	0
T2	8102	1	0	0
T3	5616	0	0	0
T4	10377	4	0	0
T5	2710	0	0	0
T6	34975	0	0	0
T7	29284	0	0	0
T8	5842	0	0	0
T9	56308	0	0	0
T10	1451	0	0	0
T11	3037	0	0	0
T24	0	36	0	0
T53	0	8	0	0
T60	0	1	0	0
T78	0	5	0	0
T79	0	6	0	0
T80	0	3	0	0
T81	0	7	0	0
T82	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50475698	12619	0	0
T1	224701	65	0	0
T2	32412	1	0	0
T3	22473	5	0	0
T4	41509	4	0	0
T5	10841	0	0	0
T6	139909	26	0	0
T7	117085	68	0	0
T8	23377	0	0	0
T9	225210	60	0	0
T10	5808	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T14	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50475698	1006	0	0
T2	32412	1	0	0
T3	22473	1	0	0
T4	41509	4	0	0
T5	10841	0	0	0
T6	139909	0	0	0
T7	117085	0	0	0
T8	23377	0	0	0
T9	225210	0	0	0
T10	5808	0	0	0
T11	12151	0	0	0
T24	0	34	0	0
T53	0	7	0	0
T54	0	2	0	0
T78	0	6	0	0
T79	0	5	0	0
T80	0	3	0	0
T81	0	8	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50475698	12619	0	0
T1	224701	65	0	0
T2	32412	1	0	0
T3	22473	5	0	0
T4	41509	4	0	0
T5	10841	0	0	0
T6	139909	26	0	0
T7	117085	68	0	0
T8	23377	0	0	0
T9	225210	60	0	0
T10	5808	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T14	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50475698	1006	0	0
T2	32412	1	0	0
T3	22473	1	0	0
T4	41509	4	0	0
T5	10841	0	0	0
T6	139909	0	0	0
T7	117085	0	0	0
T8	23377	0	0	0
T9	225210	0	0	0
T10	5808	0	0	0
T11	12151	0	0	0
T24	0	34	0	0
T53	0	7	0	0
T54	0	2	0	0
T78	0	6	0	0
T79	0	5	0	0
T80	0	3	0	0
T81	0	8	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25238720	12678	0	0
T1	112361	65	0	0
T2	16206	4	0	0
T3	11237	4	0	0
T4	20756	6	0	0
T5	5420	0	0	0
T6	69955	26	0	0
T7	58567	68	0	0
T8	11686	0	0	0
T9	112621	60	0	0
T10	2904	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T14	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25238720	1019	0	0
T2	16206	4	0	0
T3	11237	0	0	0
T4	20756	6	0	0
T5	5420	0	0	0
T6	69955	0	0	0
T7	58567	0	0	0
T8	11686	0	0	0
T9	112621	0	0	0
T10	2904	0	0	0
T11	6075	0	0	0
T24	0	41	0	0
T53	0	9	0	0
T54	0	2	0	0
T60	0	1	0	0
T79	0	7	0	0
T80	0	5	0	0
T81	0	10	0	0
T83	0	29	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25238720	12678	0	0
T1	112361	65	0	0
T2	16206	4	0	0
T3	11237	4	0	0
T4	20756	6	0	0
T5	5420	0	0	0
T6	69955	26	0	0
T7	58567	68	0	0
T8	11686	0	0	0
T9	112621	60	0	0
T10	2904	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T14	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25238720	1019	0	0
T2	16206	4	0	0
T3	11237	0	0	0
T4	20756	6	0	0
T5	5420	0	0	0
T6	69955	0	0	0
T7	58567	0	0	0
T8	11686	0	0	0
T9	112621	0	0	0
T10	2904	0	0	0
T11	6075	0	0	0
T24	0	41	0	0
T53	0	9	0	0
T54	0	2	0	0
T60	0	1	0	0
T79	0	7	0	0
T80	0	5	0	0
T81	0	10	0	0
T83	0	29	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25238705	12723	0	0
T1	112373	65	0	0
T2	16206	5	0	0
T3	11237	4	0	0
T4	20755	4	0	0
T5	5419	0	0	0
T6	69953	26	0	0
T7	58549	68	0	0
T8	11681	0	0	0
T9	112615	60	0	0
T10	2903	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T14	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25238705	1069	0	0
T2	16206	5	0	0
T3	11237	0	0	0
T4	20755	4	0	0
T5	5419	0	0	0
T6	69953	0	0	0
T7	58549	0	0	0
T8	11681	0	0	0
T9	112615	0	0	0
T10	2903	0	0	0
T11	6075	0	0	0
T24	0	35	0	0
T53	0	11	0	0
T54	0	4	0	0
T79	0	8	0	0
T80	0	5	0	0
T81	0	11	0	0
T83	0	29	0	0
T84	0	5	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25238705	12723	0	0
T1	112373	65	0	0
T2	16206	5	0	0
T3	11237	4	0	0
T4	20755	4	0	0
T5	5419	0	0	0
T6	69953	26	0	0
T7	58549	68	0	0
T8	11681	0	0	0
T9	112615	60	0	0
T10	2903	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T14	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25238705	1069	0	0
T2	16206	5	0	0
T3	11237	0	0	0
T4	20755	4	0	0
T5	5419	0	0	0
T6	69953	0	0	0
T7	58549	0	0	0
T8	11681	0	0	0
T9	112615	0	0	0
T10	2903	0	0	0
T11	6075	0	0	0
T24	0	35	0	0
T53	0	11	0	0
T54	0	4	0	0
T79	0	8	0	0
T80	0	5	0	0
T81	0	11	0	0
T83	0	29	0	0
T84	0	5	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593360	21302	0	0
T1	7037	96	0	0
T2	1011	7	0	0
T3	702	7	0	0
T4	1296	9	0	0
T5	337	2	0	0
T6	4408	42	0	0
T7	3674	76	0	0
T8	732	3	0	0
T9	7054	100	0	0
T10	181	1	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593360	1122	0	0
T2	1011	6	0	0
T3	702	1	0	0
T4	1296	8	0	0
T5	337	0	0	0
T6	4408	0	0	0
T7	3674	0	0	0
T8	732	0	0	0
T9	7054	0	0	0
T10	181	0	0	0
T11	379	0	0	0
T24	0	36	0	0
T49	0	1	0	0
T53	0	11	0	0
T54	0	4	0	0
T79	0	11	0	0
T80	0	6	0	0
T81	0	12	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593360	21302	0	0
T1	7037	96	0	0
T2	1011	7	0	0
T3	702	7	0	0
T4	1296	9	0	0
T5	337	2	0	0
T6	4408	42	0	0
T7	3674	76	0	0
T8	732	3	0	0
T9	7054	100	0	0
T10	181	1	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593360	1122	0	0
T2	1011	6	0	0
T3	702	1	0	0
T4	1296	8	0	0
T5	337	0	0	0
T6	4408	0	0	0
T7	3674	0	0	0
T8	732	0	0	0
T9	7054	0	0	0
T10	181	0	0	0
T11	379	0	0	0
T24	0	36	0	0
T49	0	1	0	0
T53	0	11	0	0
T54	0	4	0	0
T79	0	11	0	0
T80	0	6	0	0
T81	0	12	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	14197	0	0
T1	56177	75	0	0
T2	8102	6	0	0
T3	5616	4	0	0
T4	10377	9	0	0
T5	2710	0	0	0
T6	34975	29	0	0
T7	29284	75	0	0
T8	5842	0	0	0
T9	56308	75	0	0
T10	1451	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T14	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	1176	0	0
T2	8102	6	0	0
T3	5616	0	0	0
T4	10377	9	0	0
T5	2710	0	0	0
T6	34975	0	0	0
T7	29284	0	0	0
T8	5842	0	0	0
T9	56308	0	0	0
T10	1451	0	0	0
T11	3037	0	0	0
T24	0	35	0	0
T53	0	11	0	0
T54	0	5	0	0
T79	0	8	0	0
T80	0	9	0	0
T81	0	12	0	0
T83	0	30	0	0
T84	0	9	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	14197	0	0
T1	56177	75	0	0
T2	8102	6	0	0
T3	5616	4	0	0
T4	10377	9	0	0
T5	2710	0	0	0
T6	34975	29	0	0
T7	29284	75	0	0
T8	5842	0	0	0
T9	56308	75	0	0
T10	1451	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T14	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	1176	0	0
T2	8102	6	0	0
T3	5616	0	0	0
T4	10377	9	0	0
T5	2710	0	0	0
T6	34975	0	0	0
T7	29284	0	0	0
T8	5842	0	0	0
T9	56308	0	0	0
T10	1451	0	0	0
T11	3037	0	0	0
T24	0	35	0	0
T53	0	11	0	0
T54	0	5	0	0
T79	0	8	0	0
T80	0	9	0	0
T81	0	12	0	0
T83	0	30	0	0
T84	0	9	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	14247	0	0
T1	56177	75	0	0
T2	8102	8	0	0
T3	5616	4	0	0
T4	10377	10	0	0
T5	2710	0	0	0
T6	34975	29	0	0
T7	29284	75	0	0
T8	5842	0	0	0
T9	56308	75	0	0
T10	1451	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T14	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	1230	0	0
T2	8102	8	0	0
T3	5616	0	0	0
T4	10377	10	0	0
T5	2710	0	0	0
T6	34975	0	0	0
T7	29284	0	0	0
T8	5842	0	0	0
T9	56308	0	0	0
T10	1451	0	0	0
T11	3037	0	0	0
T24	0	32	0	0
T49	0	1	0	0
T53	0	13	0	0
T54	0	7	0	0
T79	0	12	0	0
T80	0	9	0	0
T81	0	12	0	0
T83	0	29	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	14247	0	0
T1	56177	75	0	0
T2	8102	8	0	0
T3	5616	4	0	0
T4	10377	10	0	0
T5	2710	0	0	0
T6	34975	29	0	0
T7	29284	75	0	0
T8	5842	0	0	0
T9	56308	75	0	0
T10	1451	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T14	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	1230	0	0
T2	8102	8	0	0
T3	5616	0	0	0
T4	10377	10	0	0
T5	2710	0	0	0
T6	34975	0	0	0
T7	29284	0	0	0
T8	5842	0	0	0
T9	56308	0	0	0
T10	1451	0	0	0
T11	3037	0	0	0
T24	0	32	0	0
T49	0	1	0	0
T53	0	13	0	0
T54	0	7	0	0
T79	0	12	0	0
T80	0	9	0	0
T81	0	12	0	0
T83	0	29	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	14285	0	0
T1	56177	75	0	0
T2	8102	9	0	0
T3	5616	4	0	0
T4	10377	12	0	0
T5	2710	0	0	0
T6	34975	29	0	0
T7	29284	75	0	0
T8	5842	0	0	0
T9	56308	75	0	0
T10	1451	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T14	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	1268	0	0
T2	8102	9	0	0
T3	5616	0	0	0
T4	10377	12	0	0
T5	2710	0	0	0
T6	34975	0	0	0
T7	29284	0	0	0
T8	5842	0	0	0
T9	56308	0	0	0
T10	1451	0	0	0
T11	3037	0	0	0
T24	0	34	0	0
T49	0	1	0	0
T53	0	10	0	0
T54	0	7	0	0
T79	0	12	0	0
T80	0	10	0	0
T81	0	14	0	0
T83	0	33	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	14285	0	0
T1	56177	75	0	0
T2	8102	9	0	0
T3	5616	4	0	0
T4	10377	12	0	0
T5	2710	0	0	0
T6	34975	29	0	0
T7	29284	75	0	0
T8	5842	0	0	0
T9	56308	75	0	0
T10	1451	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T14	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	1268	0	0
T2	8102	9	0	0
T3	5616	0	0	0
T4	10377	12	0	0
T5	2710	0	0	0
T6	34975	0	0	0
T7	29284	0	0	0
T8	5842	0	0	0
T9	56308	0	0	0
T10	1451	0	0	0
T11	3037	0	0	0
T24	0	34	0	0
T49	0	1	0	0
T53	0	10	0	0
T54	0	7	0	0
T79	0	12	0	0
T80	0	10	0	0
T81	0	14	0	0
T83	0	33	0	0