Assert Coverage for Module :
rstmgr_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
8222 |
0 |
0 |
T56 |
3951 |
9 |
0 |
0 |
T57 |
19902 |
1 |
0 |
0 |
T59 |
3787 |
13 |
0 |
0 |
T61 |
3714 |
504 |
0 |
0 |
T62 |
10079 |
355 |
0 |
0 |
T85 |
9315 |
716 |
0 |
0 |
T86 |
3129 |
437 |
0 |
0 |
T87 |
2820 |
134 |
0 |
0 |
T88 |
6071 |
338 |
0 |
0 |
T89 |
3023 |
6 |
0 |
0 |
alert_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
4419 |
0 |
0 |
T6 |
30529 |
50 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
0 |
0 |
0 |
T12 |
2348 |
0 |
0 |
0 |
T13 |
3862 |
0 |
0 |
0 |
T14 |
3544 |
0 |
0 |
0 |
T15 |
5661 |
0 |
0 |
0 |
T48 |
0 |
52 |
0 |
0 |
T95 |
0 |
174 |
0 |
0 |
T102 |
0 |
37 |
0 |
0 |
T121 |
0 |
68 |
0 |
0 |
T122 |
0 |
68 |
0 |
0 |
T123 |
0 |
24 |
0 |
0 |
T124 |
0 |
31 |
0 |
0 |
T125 |
0 |
49 |
0 |
0 |
T126 |
0 |
242 |
0 |
0 |
cpu_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
4215 |
0 |
0 |
T6 |
30529 |
30 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
0 |
0 |
0 |
T12 |
2348 |
0 |
0 |
0 |
T13 |
3862 |
0 |
0 |
0 |
T14 |
3544 |
0 |
0 |
0 |
T15 |
5661 |
0 |
0 |
0 |
T48 |
0 |
25 |
0 |
0 |
T95 |
0 |
188 |
0 |
0 |
T102 |
0 |
30 |
0 |
0 |
T121 |
0 |
47 |
0 |
0 |
T122 |
0 |
68 |
0 |
0 |
T123 |
0 |
32 |
0 |
0 |
T124 |
0 |
34 |
0 |
0 |
T125 |
0 |
42 |
0 |
0 |
T126 |
0 |
220 |
0 |
0 |
sw_rst_ctrl_n_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
8655 |
0 |
0 |
T2 |
8060 |
92 |
0 |
0 |
T3 |
5378 |
2 |
0 |
0 |
T4 |
10310 |
144 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
75 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
14 |
0 |
0 |
T48 |
0 |
52 |
0 |
0 |
T82 |
0 |
28 |
0 |
0 |
T95 |
0 |
178 |
0 |
0 |
T127 |
0 |
28 |
0 |
0 |
T128 |
0 |
41 |
0 |
0 |
sw_rst_ctrl_n_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
8501 |
0 |
0 |
T2 |
8060 |
64 |
0 |
0 |
T3 |
5378 |
11 |
0 |
0 |
T4 |
10310 |
182 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
28 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
15 |
0 |
0 |
T48 |
0 |
32 |
0 |
0 |
T82 |
0 |
29 |
0 |
0 |
T95 |
0 |
156 |
0 |
0 |
T127 |
0 |
15 |
0 |
0 |
T128 |
0 |
28 |
0 |
0 |
sw_rst_ctrl_n_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
8704 |
0 |
0 |
T2 |
8060 |
104 |
0 |
0 |
T3 |
5378 |
8 |
0 |
0 |
T4 |
10310 |
145 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
52 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
8 |
0 |
0 |
T48 |
0 |
37 |
0 |
0 |
T82 |
0 |
31 |
0 |
0 |
T95 |
0 |
196 |
0 |
0 |
T127 |
0 |
11 |
0 |
0 |
T128 |
0 |
43 |
0 |
0 |
sw_rst_ctrl_n_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
8595 |
0 |
0 |
T2 |
8060 |
83 |
0 |
0 |
T3 |
5378 |
16 |
0 |
0 |
T4 |
10310 |
125 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
70 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
17 |
0 |
0 |
T48 |
0 |
33 |
0 |
0 |
T82 |
0 |
28 |
0 |
0 |
T95 |
0 |
210 |
0 |
0 |
T127 |
0 |
9 |
0 |
0 |
T128 |
0 |
40 |
0 |
0 |
sw_rst_ctrl_n_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
8901 |
0 |
0 |
T2 |
8060 |
85 |
0 |
0 |
T3 |
5378 |
15 |
0 |
0 |
T4 |
10310 |
173 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
39 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
28 |
0 |
0 |
T48 |
0 |
67 |
0 |
0 |
T82 |
0 |
27 |
0 |
0 |
T95 |
0 |
160 |
0 |
0 |
T127 |
0 |
9 |
0 |
0 |
T128 |
0 |
55 |
0 |
0 |
sw_rst_ctrl_n_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
8373 |
0 |
0 |
T2 |
8060 |
84 |
0 |
0 |
T3 |
5378 |
0 |
0 |
0 |
T4 |
10310 |
169 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
54 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
6 |
0 |
0 |
T48 |
0 |
24 |
0 |
0 |
T82 |
0 |
22 |
0 |
0 |
T95 |
0 |
170 |
0 |
0 |
T127 |
0 |
12 |
0 |
0 |
T128 |
0 |
33 |
0 |
0 |
T129 |
0 |
21 |
0 |
0 |
sw_rst_ctrl_n_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
8982 |
0 |
0 |
T2 |
8060 |
58 |
0 |
0 |
T3 |
5378 |
12 |
0 |
0 |
T4 |
10310 |
183 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
52 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
16 |
0 |
0 |
T48 |
0 |
40 |
0 |
0 |
T82 |
0 |
11 |
0 |
0 |
T95 |
0 |
155 |
0 |
0 |
T127 |
0 |
8 |
0 |
0 |
T128 |
0 |
40 |
0 |
0 |
sw_rst_ctrl_n_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
8772 |
0 |
0 |
T2 |
8060 |
117 |
0 |
0 |
T3 |
5378 |
3 |
0 |
0 |
T4 |
10310 |
168 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
41 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
23 |
0 |
0 |
T48 |
0 |
32 |
0 |
0 |
T82 |
0 |
17 |
0 |
0 |
T95 |
0 |
163 |
0 |
0 |
T127 |
0 |
6 |
0 |
0 |
T128 |
0 |
24 |
0 |
0 |
sw_rst_regwen_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
4889 |
0 |
0 |
T2 |
8060 |
18 |
0 |
0 |
T3 |
5378 |
0 |
0 |
0 |
T4 |
10310 |
40 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
48 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
0 |
0 |
0 |
T48 |
0 |
38 |
0 |
0 |
T95 |
0 |
180 |
0 |
0 |
T102 |
0 |
30 |
0 |
0 |
T127 |
0 |
4 |
0 |
0 |
T130 |
0 |
32 |
0 |
0 |
T131 |
0 |
33 |
0 |
0 |
T132 |
0 |
24 |
0 |
0 |
sw_rst_regwen_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
4744 |
0 |
0 |
T2 |
8060 |
17 |
0 |
0 |
T3 |
5378 |
3 |
0 |
0 |
T4 |
10310 |
29 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
44 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
0 |
0 |
0 |
T48 |
0 |
44 |
0 |
0 |
T95 |
0 |
175 |
0 |
0 |
T102 |
0 |
28 |
0 |
0 |
T130 |
0 |
45 |
0 |
0 |
T131 |
0 |
27 |
0 |
0 |
T132 |
0 |
22 |
0 |
0 |
sw_rst_regwen_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
4821 |
0 |
0 |
T2 |
8060 |
21 |
0 |
0 |
T3 |
5378 |
9 |
0 |
0 |
T4 |
10310 |
35 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
41 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
0 |
0 |
0 |
T48 |
0 |
61 |
0 |
0 |
T95 |
0 |
201 |
0 |
0 |
T102 |
0 |
52 |
0 |
0 |
T127 |
0 |
13 |
0 |
0 |
T130 |
0 |
45 |
0 |
0 |
T131 |
0 |
23 |
0 |
0 |
sw_rst_regwen_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
5083 |
0 |
0 |
T2 |
8060 |
24 |
0 |
0 |
T3 |
5378 |
12 |
0 |
0 |
T4 |
10310 |
26 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
43 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
0 |
0 |
0 |
T48 |
0 |
39 |
0 |
0 |
T95 |
0 |
148 |
0 |
0 |
T102 |
0 |
31 |
0 |
0 |
T127 |
0 |
7 |
0 |
0 |
T130 |
0 |
35 |
0 |
0 |
T131 |
0 |
26 |
0 |
0 |
sw_rst_regwen_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
4694 |
0 |
0 |
T2 |
8060 |
31 |
0 |
0 |
T3 |
5378 |
7 |
0 |
0 |
T4 |
10310 |
37 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
42 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
0 |
0 |
0 |
T48 |
0 |
62 |
0 |
0 |
T95 |
0 |
182 |
0 |
0 |
T102 |
0 |
51 |
0 |
0 |
T127 |
0 |
5 |
0 |
0 |
T130 |
0 |
30 |
0 |
0 |
T131 |
0 |
30 |
0 |
0 |
sw_rst_regwen_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
4619 |
0 |
0 |
T2 |
8060 |
7 |
0 |
0 |
T3 |
5378 |
3 |
0 |
0 |
T4 |
10310 |
25 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
49 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
0 |
0 |
0 |
T48 |
0 |
35 |
0 |
0 |
T95 |
0 |
179 |
0 |
0 |
T102 |
0 |
44 |
0 |
0 |
T127 |
0 |
11 |
0 |
0 |
T130 |
0 |
28 |
0 |
0 |
T131 |
0 |
39 |
0 |
0 |
sw_rst_regwen_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
4697 |
0 |
0 |
T2 |
8060 |
15 |
0 |
0 |
T3 |
5378 |
8 |
0 |
0 |
T4 |
10310 |
24 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
54 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
0 |
0 |
0 |
T48 |
0 |
44 |
0 |
0 |
T95 |
0 |
182 |
0 |
0 |
T102 |
0 |
36 |
0 |
0 |
T127 |
0 |
9 |
0 |
0 |
T130 |
0 |
25 |
0 |
0 |
T131 |
0 |
30 |
0 |
0 |
sw_rst_regwen_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12030095 |
4687 |
0 |
0 |
T2 |
8060 |
2 |
0 |
0 |
T3 |
5378 |
3 |
0 |
0 |
T4 |
10310 |
29 |
0 |
0 |
T5 |
2523 |
0 |
0 |
0 |
T6 |
30529 |
51 |
0 |
0 |
T7 |
25972 |
0 |
0 |
0 |
T8 |
5488 |
0 |
0 |
0 |
T9 |
52938 |
0 |
0 |
0 |
T10 |
1408 |
0 |
0 |
0 |
T11 |
2540 |
0 |
0 |
0 |
T48 |
0 |
43 |
0 |
0 |
T95 |
0 |
218 |
0 |
0 |
T102 |
0 |
47 |
0 |
0 |
T127 |
0 |
8 |
0 |
0 |
T130 |
0 |
35 |
0 |
0 |
T131 |
0 |
25 |
0 |
0 |