Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T12
0	1	Covered	T6,T24,T25
1	0	Covered	T3,T6,T24

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T3,T6,T12
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52580421	8468	0	0
CascadeEffAonToRstPorAboveRise_A	52580421	8468	0	0
CascadeEffAonToRstPorIoAboveFall_A	50475698	8468	0	0
CascadeEffAonToRstPorIoAboveRise_A	50475698	8468	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25238720	8468	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25238720	8468	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12619161	8468	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12619161	8468	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25238705	8468	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25238705	8468	0	0
CascadeLcToLcAboveFall_A	52580421	21524	0	0
CascadeLcToLcAboveRise_A	52580421	21524	0	0
CascadeLcToLcAonAboveFall_A	1593360	21524	0	0
CascadeLcToLcAonAboveRise_A	1593360	21524	0	0
CascadeLcToLcShadowedAboveFall_A	52580421	21524	0	0
CascadeLcToLcShadowedAboveRise_A	52580421	21524	0	0
CascadePorToAonAboveFall_A	1593360	6729	0	0
CascadeSysToSysAboveFall_A	52580421	21524	0	0
CascadeSysToSysAboveRise_A	52580421	21524	0	0
ScanRstToAonRise_A	1593360	193	0	0
StablePorToAonRise_A	1593360	8468	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11208681	21524	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11208681	21524	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11208681	21524	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11208681	21524	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12619161	21524	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12619161	21524	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11208681	21524	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11208681	21524	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11208681	21524	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11208681	21524	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52580421	8468	0	0
T1	234067	27	0	0
T2	33763	1	0	0
T3	23417	2	0	0
T4	43240	1	0	0
T5	11293	2	0	0
T6	145756	14	0	0
T7	121987	27	0	0
T8	24330	8	0	0
T9	234637	27	0	0
T10	6051	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52580421	8468	0	0
T1	234067	27	0	0
T2	33763	1	0	0
T3	23417	2	0	0
T4	43240	1	0	0
T5	11293	2	0	0
T6	145756	14	0	0
T7	121987	27	0	0
T8	24330	8	0	0
T9	234637	27	0	0
T10	6051	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50475698	8468	0	0
T1	224701	27	0	0
T2	32412	1	0	0
T3	22473	2	0	0
T4	41509	1	0	0
T5	10841	2	0	0
T6	139909	14	0	0
T7	117085	27	0	0
T8	23377	8	0	0
T9	225210	27	0	0
T10	5808	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50475698	8468	0	0
T1	224701	27	0	0
T2	32412	1	0	0
T3	22473	2	0	0
T4	41509	1	0	0
T5	10841	2	0	0
T6	139909	14	0	0
T7	117085	27	0	0
T8	23377	8	0	0
T9	225210	27	0	0
T10	5808	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25238720	8468	0	0
T1	112361	27	0	0
T2	16206	1	0	0
T3	11237	2	0	0
T4	20756	1	0	0
T5	5420	2	0	0
T6	69955	14	0	0
T7	58567	27	0	0
T8	11686	8	0	0
T9	112621	27	0	0
T10	2904	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25238720	8468	0	0
T1	112361	27	0	0
T2	16206	1	0	0
T3	11237	2	0	0
T4	20756	1	0	0
T5	5420	2	0	0
T6	69955	14	0	0
T7	58567	27	0	0
T8	11686	8	0	0
T9	112621	27	0	0
T10	2904	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	8468	0	0
T1	56177	27	0	0
T2	8102	1	0	0
T3	5616	2	0	0
T4	10377	1	0	0
T5	2710	2	0	0
T6	34975	14	0	0
T7	29284	27	0	0
T8	5842	8	0	0
T9	56308	27	0	0
T10	1451	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	8468	0	0
T1	56177	27	0	0
T2	8102	1	0	0
T3	5616	2	0	0
T4	10377	1	0	0
T5	2710	2	0	0
T6	34975	14	0	0
T7	29284	27	0	0
T8	5842	8	0	0
T9	56308	27	0	0
T10	1451	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25238705	8468	0	0
T1	112373	27	0	0
T2	16206	1	0	0
T3	11237	2	0	0
T4	20755	1	0	0
T5	5419	2	0	0
T6	69953	14	0	0
T7	58549	27	0	0
T8	11681	8	0	0
T9	112615	27	0	0
T10	2903	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25238705	8468	0	0
T1	112373	27	0	0
T2	16206	1	0	0
T3	11237	2	0	0
T4	20755	1	0	0
T5	5419	2	0	0
T6	69953	14	0	0
T7	58549	27	0	0
T8	11681	8	0	0
T9	112615	27	0	0
T10	2903	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52580421	21524	0	0
T1	234067	102	0	0
T2	33763	1	0	0
T3	23417	6	0	0
T4	43240	1	0	0
T5	11293	2	0	0
T6	145756	43	0	0
T7	121987	102	0	0
T8	24330	8	0	0
T9	234637	102	0	0
T10	6051	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52580421	21524	0	0
T1	234067	102	0	0
T2	33763	1	0	0
T3	23417	6	0	0
T4	43240	1	0	0
T5	11293	2	0	0
T6	145756	43	0	0
T7	121987	102	0	0
T8	24330	8	0	0
T9	234637	102	0	0
T10	6051	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593360	21524	0	0
T1	7037	102	0	0
T2	1011	1	0	0
T3	702	6	0	0
T4	1296	1	0	0
T5	337	2	0	0
T6	4408	43	0	0
T7	3674	102	0	0
T8	732	8	0	0
T9	7054	102	0	0
T10	181	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593360	21524	0	0
T1	7037	102	0	0
T2	1011	1	0	0
T3	702	6	0	0
T4	1296	1	0	0
T5	337	2	0	0
T6	4408	43	0	0
T7	3674	102	0	0
T8	732	8	0	0
T9	7054	102	0	0
T10	181	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52580421	21524	0	0
T1	234067	102	0	0
T2	33763	1	0	0
T3	23417	6	0	0
T4	43240	1	0	0
T5	11293	2	0	0
T6	145756	43	0	0
T7	121987	102	0	0
T8	24330	8	0	0
T9	234637	102	0	0
T10	6051	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52580421	21524	0	0
T1	234067	102	0	0
T2	33763	1	0	0
T3	23417	6	0	0
T4	43240	1	0	0
T5	11293	2	0	0
T6	145756	43	0	0
T7	121987	102	0	0
T8	24330	8	0	0
T9	234637	102	0	0
T10	6051	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593360	6729	0	0
T1	7037	27	0	0
T2	1011	1	0	0
T3	702	1	0	0
T4	1296	1	0	0
T5	337	7	0	0
T6	4408	9	0	0
T7	3674	27	0	0
T8	732	8	0	0
T9	7054	27	0	0
T10	181	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52580421	21524	0	0
T1	234067	102	0	0
T2	33763	1	0	0
T3	23417	6	0	0
T4	43240	1	0	0
T5	11293	2	0	0
T6	145756	43	0	0
T7	121987	102	0	0
T8	24330	8	0	0
T9	234637	102	0	0
T10	6051	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52580421	21524	0	0
T1	234067	102	0	0
T2	33763	1	0	0
T3	23417	6	0	0
T4	43240	1	0	0
T5	11293	2	0	0
T6	145756	43	0	0
T7	121987	102	0	0
T8	24330	8	0	0
T9	234637	102	0	0
T10	6051	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593360	193	0	0
T24	12025	3	0	0
T25	497	0	0	0
T35	2303	0	0	0
T42	5681	0	0	0
T46	243	0	0	0
T47	462	0	0	0
T48	4312	1	0	0
T49	340	0	0	0
T77	312	1	0	0
T78	495	0	0	0
T83	0	8	0	0
T93	0	1	0	0
T95	0	2	0	0
T96	0	10	0	0
T97	0	1	0	0
T134	0	1	0	0
T135	0	7	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593360	8468	0	0
T1	7037	27	0	0
T2	1011	1	0	0
T3	702	2	0	0
T4	1296	1	0	0
T5	337	2	0	0
T6	4408	14	0	0
T7	3674	27	0	0
T8	732	8	0	0
T9	7054	27	0	0
T10	181	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11208681	21524	0	0
T1	52829	102	0	0
T2	8060	1	0	0
T3	5378	6	0	0
T4	10310	1	0	0
T5	2523	2	0	0
T6	30529	43	0	0
T7	25972	102	0	0
T8	5488	8	0	0
T9	52938	102	0	0
T10	1408	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11208681	21524	0	0
T1	52829	102	0	0
T2	8060	1	0	0
T3	5378	6	0	0
T4	10310	1	0	0
T5	2523	2	0	0
T6	30529	43	0	0
T7	25972	102	0	0
T8	5488	8	0	0
T9	52938	102	0	0
T10	1408	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11208681	21524	0	0
T1	52829	102	0	0
T2	8060	1	0	0
T3	5378	6	0	0
T4	10310	1	0	0
T5	2523	2	0	0
T6	30529	43	0	0
T7	25972	102	0	0
T8	5488	8	0	0
T9	52938	102	0	0
T10	1408	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11208681	21524	0	0
T1	52829	102	0	0
T2	8060	1	0	0
T3	5378	6	0	0
T4	10310	1	0	0
T5	2523	2	0	0
T6	30529	43	0	0
T7	25972	102	0	0
T8	5488	8	0	0
T9	52938	102	0	0
T10	1408	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	21524	0	0
T1	56177	102	0	0
T2	8102	1	0	0
T3	5616	6	0	0
T4	10377	1	0	0
T5	2710	2	0	0
T6	34975	43	0	0
T7	29284	102	0	0
T8	5842	8	0	0
T9	56308	102	0	0
T10	1451	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12619161	21524	0	0
T1	56177	102	0	0
T2	8102	1	0	0
T3	5616	6	0	0
T4	10377	1	0	0
T5	2710	2	0	0
T6	34975	43	0	0
T7	29284	102	0	0
T8	5842	8	0	0
T9	56308	102	0	0
T10	1451	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11208681	21524	0	0
T1	52829	102	0	0
T2	8060	1	0	0
T3	5378	6	0	0
T4	10310	1	0	0
T5	2523	2	0	0
T6	30529	43	0	0
T7	25972	102	0	0
T8	5488	8	0	0
T9	52938	102	0	0
T10	1408	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11208681	21524	0	0
T1	52829	102	0	0
T2	8060	1	0	0
T3	5378	6	0	0
T4	10310	1	0	0
T5	2523	2	0	0
T6	30529	43	0	0
T7	25972	102	0	0
T8	5488	8	0	0
T9	52938	102	0	0
T10	1408	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11208681	21524	0	0
T1	52829	102	0	0
T2	8060	1	0	0
T3	5378	6	0	0
T4	10310	1	0	0
T5	2523	2	0	0
T6	30529	43	0	0
T7	25972	102	0	0
T8	5488	8	0	0
T9	52938	102	0	0
T10	1408	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11208681	21524	0	0
T1	52829	102	0	0
T2	8060	1	0	0
T3	5378	6	0	0
T4	10310	1	0	0
T5	2523	2	0	0
T6	30529	43	0	0
T7	25972	102	0	0
T8	5488	8	0	0
T9	52938	102	0	0
T10	1408	1	0	0