Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	657370	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

394159

1

T1

314

T2

809

T5

129

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	562116	1			T1	419		T2	1250		T3	1
values[0x0]	244669	1			T1	205		T2	475		T5	92
values[0x1]	244744	1			T1	168		T2	504		T5	101

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	551819	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

499710

1

T1

382

T2

1054

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3803	1			T1	70		T2	16		T5	3
valid_sources[0x01]	3794	1			T2	10		T6	17		T14	10
valid_sources[0x02]	6818	1			T1	7		T2	3		T5	1
valid_sources[0x03]	3487	1			T2	7		T5	2		T6	11
valid_sources[0x04]	4142	1			T2	12		T6	14		T14	8
valid_sources[0x05]	3910	1			T2	10		T6	9		T8	1
valid_sources[0x06]	3491	1			T2	6		T5	1		T6	9
valid_sources[0x07]	4926	1			T2	7		T5	1		T6	8
valid_sources[0x08]	4229	1			T2	9		T6	22		T8	1
valid_sources[0x09]	3898	1			T2	11		T5	2		T6	13
valid_sources[0x0a]	3700	1			T2	10		T5	1		T6	13
valid_sources[0x0b]	3505	1			T2	11		T5	4		T6	7
valid_sources[0x0c]	3650	1			T2	8		T5	1		T6	8
valid_sources[0x0d]	3437	1			T2	17		T6	13		T8	3
valid_sources[0x0e]	3331	1			T2	6		T6	4		T9	9
valid_sources[0x0f]	3982	1			T2	13		T5	2		T6	12
valid_sources[0x10]	4075	1			T2	9		T5	2		T6	16
valid_sources[0x11]	3812	1			T2	9		T5	4		T6	15
valid_sources[0x12]	3986	1			T2	14		T6	15		T14	8
valid_sources[0x13]	3715	1			T2	21		T5	1		T6	15
valid_sources[0x14]	3571	1			T2	11		T5	3		T6	7
valid_sources[0x15]	4370	1			T2	12		T6	10		T8	24
valid_sources[0x16]	7542	1			T2	7		T5	2		T6	10
valid_sources[0x17]	3578	1			T2	8		T5	1		T6	11
valid_sources[0x18]	3734	1			T2	5		T5	2		T6	13
valid_sources[0x19]	3503	1			T2	8		T5	1		T6	15
valid_sources[0x1a]	3972	1			T2	4		T5	1		T6	17
valid_sources[0x1b]	3731	1			T2	18		T6	11		T14	14
valid_sources[0x1c]	3982	1			T2	12		T6	13		T8	15
valid_sources[0x1d]	3962	1			T2	8		T6	17		T8	5
valid_sources[0x1e]	3811	1			T2	7		T6	16		T14	7
valid_sources[0x1f]	3826	1			T2	13		T5	1		T6	15
valid_sources[0x20]	3531	1			T2	10		T6	7		T14	19
valid_sources[0x21]	3589	1			T2	10		T6	8		T14	9
valid_sources[0x22]	3446	1			T2	5		T5	1		T6	14
valid_sources[0x23]	3536	1			T1	45		T2	7		T6	12
valid_sources[0x24]	4529	1			T1	28		T2	18		T5	2
valid_sources[0x25]	3365	1			T1	8		T2	13		T6	16
valid_sources[0x26]	4498	1			T2	5		T6	10		T8	17
valid_sources[0x27]	3512	1			T2	12		T5	3		T6	15
valid_sources[0x28]	4246	1			T2	10		T5	4		T6	10
valid_sources[0x29]	3842	1			T2	11		T5	4		T6	11
valid_sources[0x2a]	4351	1			T2	10		T5	2		T6	4
valid_sources[0x2b]	4868	1			T2	9		T5	1		T6	13
valid_sources[0x2c]	4982	1			T2	13		T5	3		T6	9
valid_sources[0x2d]	6648	1			T2	4		T5	4		T6	13
valid_sources[0x2e]	3869	1			T1	42		T2	4		T5	5
valid_sources[0x2f]	4231	1			T2	8		T5	1		T6	8
valid_sources[0x30]	3938	1			T2	10		T5	2		T6	13
valid_sources[0x31]	3520	1			T2	5		T5	1		T6	10
valid_sources[0x32]	4651	1			T2	7		T6	11		T8	22
valid_sources[0x33]	4203	1			T2	6		T6	14		T8	12
valid_sources[0x34]	3897	1			T1	8		T2	5		T6	13
valid_sources[0x35]	6805	1			T2	7		T5	3		T6	12
valid_sources[0x36]	3500	1			T2	4		T6	6		T14	12
valid_sources[0x37]	3927	1			T2	7		T5	3		T6	12
valid_sources[0x38]	3633	1			T2	7		T6	11		T14	12
valid_sources[0x39]	6087	1			T2	9		T5	2		T6	13
valid_sources[0x3a]	3442	1			T2	12		T5	1		T6	15
valid_sources[0x3b]	3832	1			T2	13		T5	4		T6	12
valid_sources[0x3c]	3829	1			T2	2		T5	1		T6	14
valid_sources[0x3d]	3557	1			T2	19		T5	1		T6	9
valid_sources[0x3e]	4029	1			T2	16		T6	14		T8	34
valid_sources[0x3f]	4110	1			T2	20		T5	6		T6	14
valid_sources[0x40]	3752	1			T2	14		T5	9		T6	14
valid_sources[0x41]	4084	1			T2	13		T5	1		T6	11
valid_sources[0x42]	3472	1			T2	5		T5	3		T6	15
valid_sources[0x43]	4705	1			T2	4		T6	11		T8	9
valid_sources[0x44]	4294	1			T2	14		T5	1		T6	11
valid_sources[0x45]	3745	1			T2	4		T5	4		T6	15
valid_sources[0x46]	3800	1			T2	7		T3	1		T6	7
valid_sources[0x47]	4163	1			T2	8		T6	11		T14	11
valid_sources[0x48]	4953	1			T2	9		T6	15		T9	1
valid_sources[0x49]	4334	1			T2	5		T5	1		T6	20
valid_sources[0x4a]	3456	1			T2	5		T5	1		T6	11
valid_sources[0x4b]	3472	1			T2	4		T6	8		T14	8
valid_sources[0x4c]	4558	1			T1	1		T2	13		T5	3
valid_sources[0x4d]	3761	1			T2	7		T6	21		T8	8
valid_sources[0x4e]	3263	1			T2	12		T6	15		T14	7
valid_sources[0x4f]	4086	1			T1	2		T2	10		T5	1
valid_sources[0x50]	3903	1			T2	9		T5	1		T6	17
valid_sources[0x51]	3626	1			T2	10		T5	1		T6	9
valid_sources[0x52]	4737	1			T2	7		T5	1		T6	8
valid_sources[0x53]	3973	1			T2	14		T5	1		T6	12
valid_sources[0x54]	5312	1			T2	15		T5	1		T6	7
valid_sources[0x55]	3951	1			T2	6		T5	1		T6	15
valid_sources[0x56]	4469	1			T2	8		T5	4		T6	12
valid_sources[0x57]	3341	1			T1	7		T2	12		T5	1
valid_sources[0x58]	3776	1			T2	9		T6	11		T14	13
valid_sources[0x59]	3765	1			T2	13		T5	1		T6	10
valid_sources[0x5a]	3506	1			T2	11		T6	10		T14	10
valid_sources[0x5b]	3613	1			T2	12		T6	10		T14	16
valid_sources[0x5c]	4485	1			T2	12		T5	1		T6	14
valid_sources[0x5d]	3848	1			T2	9		T5	1		T6	11
valid_sources[0x5e]	3580	1			T2	12		T5	1		T6	12
valid_sources[0x5f]	3694	1			T2	19		T5	3		T6	18
valid_sources[0x60]	4191	1			T2	9		T6	8		T14	12
valid_sources[0x61]	3315	1			T2	11		T6	12		T14	7
valid_sources[0x62]	6691	1			T2	13		T5	1		T6	8
valid_sources[0x63]	3509	1			T2	10		T5	1		T6	20
valid_sources[0x64]	4826	1			T2	6		T6	14		T8	31
valid_sources[0x65]	4954	1			T2	2		T6	11		T12	18
valid_sources[0x66]	4715	1			T2	6		T6	12		T14	16
valid_sources[0x67]	3676	1			T2	6		T5	3		T6	10
valid_sources[0x68]	3594	1			T2	10		T6	14		T14	12
valid_sources[0x69]	3518	1			T2	10		T5	3		T6	14
valid_sources[0x6a]	3581	1			T2	14		T5	6		T6	8
valid_sources[0x6b]	4071	1			T2	10		T5	4		T6	14
valid_sources[0x6c]	3366	1			T2	5		T6	12		T8	9
valid_sources[0x6d]	3460	1			T2	3		T6	14		T14	15
valid_sources[0x6e]	4081	1			T1	14		T2	14		T5	1
valid_sources[0x6f]	3867	1			T1	110		T2	4		T6	16
valid_sources[0x70]	4008	1			T2	3		T6	13		T8	2
valid_sources[0x71]	3744	1			T2	6		T5	5		T6	15
valid_sources[0x72]	3383	1			T2	9		T5	2		T6	9
valid_sources[0x73]	3813	1			T2	5		T5	1		T6	7
valid_sources[0x74]	3503	1			T2	12		T6	16		T14	6
valid_sources[0x75]	5626	1			T2	14		T5	1		T6	7
valid_sources[0x76]	3352	1			T2	4		T5	2		T6	19
valid_sources[0x77]	4333	1			T2	7		T6	14		T8	8
valid_sources[0x78]	3764	1			T2	8		T6	8		T8	9
valid_sources[0x79]	3776	1			T2	4		T5	2		T6	10
valid_sources[0x7a]	4182	1			T2	6		T6	11		T8	3
valid_sources[0x7b]	4450	1			T1	45		T2	16		T5	7
valid_sources[0x7c]	3517	1			T2	7		T5	1		T6	10
valid_sources[0x7d]	4059	1			T2	9		T5	3		T6	15
valid_sources[0x7e]	4338	1			T2	7		T6	11		T8	2
valid_sources[0x7f]	3954	1			T2	5		T6	13		T13	379
valid_sources[0x80]	3835	1			T2	7		T5	2		T6	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

263498

1

T1

210

T2

583

T5

84

values[0x0]

all_enables

biggest_size

85159

1

T1

80

T2

156

T5

28

values[0x1]

all_enables

biggest_size

45502

1

T1

24

T2

70

T5

17