Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T8
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T11
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T11
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T8
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T11
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T8
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13429862	14818	0	0
gen_assertions[0].RstEnOn_A	13429862	1172	0	0
gen_assertions[0].RstNOff_A	13429862	14818	0	0
gen_assertions[0].RstNOn_A	13429862	1172	0	0
gen_assertions[1].RstEnOff_A	53718484	13404	0	0
gen_assertions[1].RstEnOn_A	53718484	1074	0	0
gen_assertions[1].RstNOff_A	53718484	13404	0	0
gen_assertions[1].RstNOn_A	53718484	1074	0	0
gen_assertions[2].RstEnOff_A	26860412	13447	0	0
gen_assertions[2].RstEnOn_A	26860412	1080	0	0
gen_assertions[2].RstNOff_A	26860412	13447	0	0
gen_assertions[2].RstNOn_A	26860412	1080	0	0
gen_assertions[3].RstEnOff_A	26860317	13509	0	0
gen_assertions[3].RstEnOn_A	26860317	1121	0	0
gen_assertions[3].RstNOff_A	26860317	13509	0	0
gen_assertions[3].RstNOn_A	26860317	1121	0	0
gen_assertions[4].RstEnOff_A	1696633	22669	0	0
gen_assertions[4].RstEnOn_A	1696633	1134	0	0
gen_assertions[4].RstNOff_A	1696633	22669	0	0
gen_assertions[4].RstNOn_A	1696633	1134	0	0
gen_assertions[5].RstEnOff_A	13429862	15017	0	0
gen_assertions[5].RstEnOn_A	13429862	1210	0	0
gen_assertions[5].RstNOff_A	13429862	15017	0	0
gen_assertions[5].RstNOn_A	13429862	1210	0	0
gen_assertions[6].RstEnOff_A	13429862	15079	0	0
gen_assertions[6].RstEnOn_A	13429862	1257	0	0
gen_assertions[6].RstNOff_A	13429862	15079	0	0
gen_assertions[6].RstNOn_A	13429862	1257	0	0
gen_assertions[7].RstEnOff_A	13429862	15118	0	0
gen_assertions[7].RstEnOn_A	13429862	1301	0	0
gen_assertions[7].RstNOff_A	13429862	15118	0	0
gen_assertions[7].RstNOn_A	13429862	1301	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	14818	0	0
T1	2876	2	0	0
T2	35282	28	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	5	0	0
T6	29248	75	0	0
T7	4208	4	0	0
T8	3583	6	0	0
T9	2657	5	0	0
T10	5838	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	1172	0	0
T1	2876	2	0	0
T2	35282	0	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	1	0	0
T6	29248	0	0	0
T7	4208	0	0	0
T8	3583	6	0	0
T9	2657	1	0	0
T10	5838	0	0	0
T11	0	5	0	0
T13	0	1	0	0
T41	0	2	0	0
T45	0	4	0	0
T46	0	1	0	0
T48	0	31	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	14818	0	0
T1	2876	2	0	0
T2	35282	28	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	5	0	0
T6	29248	75	0	0
T7	4208	4	0	0
T8	3583	6	0	0
T9	2657	5	0	0
T10	5838	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	1172	0	0
T1	2876	2	0	0
T2	35282	0	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	1	0	0
T6	29248	0	0	0
T7	4208	0	0	0
T8	3583	6	0	0
T9	2657	1	0	0
T10	5838	0	0	0
T11	0	5	0	0
T13	0	1	0	0
T41	0	2	0	0
T45	0	4	0	0
T46	0	1	0	0
T48	0	31	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53718484	13404	0	0
T1	11504	3	0	0
T2	141111	24	0	0
T3	20240	0	0	0
T4	14177	0	0	0
T5	11669	4	0	0
T6	116956	66	0	0
T7	16832	4	0	0
T8	14332	7	0	0
T9	10628	4	0	0
T10	23347	0	0	0
T11	0	6	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53718484	1074	0	0
T1	11504	3	0	0
T2	141111	0	0	0
T3	20240	0	0	0
T4	14177	0	0	0
T5	11669	0	0	0
T6	116956	0	0	0
T7	16832	0	0	0
T8	14332	7	0	0
T9	10628	0	0	0
T10	23347	0	0	0
T11	0	6	0	0
T41	0	3	0	0
T48	0	30	0	0
T86	0	21	0	0
T87	0	2	0	0
T88	0	3	0	0
T89	0	4	0	0
T90	0	17	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53718484	13404	0	0
T1	11504	3	0	0
T2	141111	24	0	0
T3	20240	0	0	0
T4	14177	0	0	0
T5	11669	4	0	0
T6	116956	66	0	0
T7	16832	4	0	0
T8	14332	7	0	0
T9	10628	4	0	0
T10	23347	0	0	0
T11	0	6	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53718484	1074	0	0
T1	11504	3	0	0
T2	141111	0	0	0
T3	20240	0	0	0
T4	14177	0	0	0
T5	11669	0	0	0
T6	116956	0	0	0
T7	16832	0	0	0
T8	14332	7	0	0
T9	10628	0	0	0
T10	23347	0	0	0
T11	0	6	0	0
T41	0	3	0	0
T48	0	30	0	0
T86	0	21	0	0
T87	0	2	0	0
T88	0	3	0	0
T89	0	4	0	0
T90	0	17	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26860412	13447	0	0
T1	5753	5	0	0
T2	70551	24	0	0
T3	10120	0	0	0
T4	7088	0	0	0
T5	5833	4	0	0
T6	58495	66	0	0
T7	8418	4	0	0
T8	7166	7	0	0
T9	5315	4	0	0
T10	11675	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26860412	1080	0	0
T1	5753	5	0	0
T2	70551	0	0	0
T3	10120	0	0	0
T4	7088	0	0	0
T5	5833	0	0	0
T6	58495	0	0	0
T7	8418	0	0	0
T8	7166	7	0	0
T9	5315	0	0	0
T10	11675	0	0	0
T11	0	5	0	0
T41	0	2	0	0
T48	0	29	0	0
T86	0	19	0	0
T87	0	3	0	0
T88	0	4	0	0
T90	0	19	0	0
T91	0	4	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26860412	13447	0	0
T1	5753	5	0	0
T2	70551	24	0	0
T3	10120	0	0	0
T4	7088	0	0	0
T5	5833	4	0	0
T6	58495	66	0	0
T7	8418	4	0	0
T8	7166	7	0	0
T9	5315	4	0	0
T10	11675	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26860412	1080	0	0
T1	5753	5	0	0
T2	70551	0	0	0
T3	10120	0	0	0
T4	7088	0	0	0
T5	5833	0	0	0
T6	58495	0	0	0
T7	8418	0	0	0
T8	7166	7	0	0
T9	5315	0	0	0
T10	11675	0	0	0
T11	0	5	0	0
T41	0	2	0	0
T48	0	29	0	0
T86	0	19	0	0
T87	0	3	0	0
T88	0	4	0	0
T90	0	19	0	0
T91	0	4	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26860317	13509	0	0
T1	5752	6	0	0
T2	70553	24	0	0
T3	10120	0	0	0
T4	7088	0	0	0
T5	5835	5	0	0
T6	58486	66	0	0
T7	8413	4	0	0
T8	7166	7	0	0
T9	5315	4	0	0
T10	11672	0	0	0
T11	0	6	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26860317	1121	0	0
T1	5752	6	0	0
T2	70553	0	0	0
T3	10120	0	0	0
T4	7088	0	0	0
T5	5835	1	0	0
T6	58486	0	0	0
T7	8413	0	0	0
T8	7166	7	0	0
T9	5315	0	0	0
T10	11672	0	0	0
T11	0	6	0	0
T23	0	1	0	0
T41	0	3	0	0
T48	0	26	0	0
T86	0	20	0	0
T87	0	5	0	0
T88	0	3	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26860317	13509	0	0
T1	5752	6	0	0
T2	70553	24	0	0
T3	10120	0	0	0
T4	7088	0	0	0
T5	5835	5	0	0
T6	58486	66	0	0
T7	8413	4	0	0
T8	7166	7	0	0
T9	5315	4	0	0
T10	11672	0	0	0
T11	0	6	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26860317	1121	0	0
T1	5752	6	0	0
T2	70553	0	0	0
T3	10120	0	0	0
T4	7088	0	0	0
T5	5835	1	0	0
T6	58486	0	0	0
T7	8413	0	0	0
T8	7166	7	0	0
T9	5315	0	0	0
T10	11672	0	0	0
T11	0	6	0	0
T23	0	1	0	0
T41	0	3	0	0
T48	0	26	0	0
T86	0	20	0	0
T87	0	5	0	0
T88	0	3	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696633	22669	0	0
T1	357	6	0	0
T2	4458	43	0	0
T3	631	2	0	0
T4	443	2	0	0
T5	364	6	0	0
T6	3670	75	0	0
T7	524	6	0	0
T8	447	11	0	0
T9	332	7	0	0
T10	731	3	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696633	1134	0	0
T1	357	5	0	0
T2	4458	0	0	0
T3	631	0	0	0
T4	443	0	0	0
T5	364	0	0	0
T6	3670	0	0	0
T7	524	0	0	0
T8	447	10	0	0
T9	332	1	0	0
T10	731	0	0	0
T11	0	8	0	0
T23	0	1	0	0
T41	0	4	0	0
T48	0	26	0	0
T86	0	21	0	0
T87	0	5	0	0
T88	0	5	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696633	22669	0	0
T1	357	6	0	0
T2	4458	43	0	0
T3	631	2	0	0
T4	443	2	0	0
T5	364	6	0	0
T6	3670	75	0	0
T7	524	6	0	0
T8	447	11	0	0
T9	332	7	0	0
T10	731	3	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696633	1134	0	0
T1	357	5	0	0
T2	4458	0	0	0
T3	631	0	0	0
T4	443	0	0	0
T5	364	0	0	0
T6	3670	0	0	0
T7	524	0	0	0
T8	447	10	0	0
T9	332	1	0	0
T10	731	0	0	0
T11	0	8	0	0
T23	0	1	0	0
T41	0	4	0	0
T48	0	26	0	0
T86	0	21	0	0
T87	0	5	0	0
T88	0	5	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	15017	0	0
T1	2876	6	0	0
T2	35282	28	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	4	0	0
T6	29248	75	0	0
T7	4208	4	0	0
T8	3583	10	0	0
T9	2657	5	0	0
T10	5838	0	0	0
T11	0	9	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	1210	0	0
T1	2876	6	0	0
T2	35282	0	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	0	0	0
T6	29248	0	0	0
T7	4208	0	0	0
T8	3583	10	0	0
T9	2657	1	0	0
T10	5838	0	0	0
T11	0	9	0	0
T41	0	3	0	0
T48	0	26	0	0
T86	0	21	0	0
T87	0	7	0	0
T88	0	6	0	0
T90	0	19	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	15017	0	0
T1	2876	6	0	0
T2	35282	28	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	4	0	0
T6	29248	75	0	0
T7	4208	4	0	0
T8	3583	10	0	0
T9	2657	5	0	0
T10	5838	0	0	0
T11	0	9	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	1210	0	0
T1	2876	6	0	0
T2	35282	0	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	0	0	0
T6	29248	0	0	0
T7	4208	0	0	0
T8	3583	10	0	0
T9	2657	1	0	0
T10	5838	0	0	0
T11	0	9	0	0
T41	0	3	0	0
T48	0	26	0	0
T86	0	21	0	0
T87	0	7	0	0
T88	0	6	0	0
T90	0	19	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	15079	0	0
T1	2876	8	0	0
T2	35282	28	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	4	0	0
T6	29248	75	0	0
T7	4208	4	0	0
T8	3583	12	0	0
T9	2657	4	0	0
T10	5838	0	0	0
T11	0	10	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	1257	0	0
T1	2876	8	0	0
T2	35282	0	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	0	0	0
T6	29248	0	0	0
T7	4208	0	0	0
T8	3583	12	0	0
T9	2657	0	0	0
T10	5838	0	0	0
T11	0	10	0	0
T41	0	4	0	0
T48	0	28	0	0
T86	0	18	0	0
T87	0	7	0	0
T88	0	8	0	0
T90	0	16	0	0
T91	0	11	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	15079	0	0
T1	2876	8	0	0
T2	35282	28	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	4	0	0
T6	29248	75	0	0
T7	4208	4	0	0
T8	3583	12	0	0
T9	2657	4	0	0
T10	5838	0	0	0
T11	0	10	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	1257	0	0
T1	2876	8	0	0
T2	35282	0	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	0	0	0
T6	29248	0	0	0
T7	4208	0	0	0
T8	3583	12	0	0
T9	2657	0	0	0
T10	5838	0	0	0
T11	0	10	0	0
T41	0	4	0	0
T48	0	28	0	0
T86	0	18	0	0
T87	0	7	0	0
T88	0	8	0	0
T90	0	16	0	0
T91	0	11	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	15118	0	0
T1	2876	9	0	0
T2	35282	28	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	5	0	0
T6	29248	75	0	0
T7	4208	4	0	0
T8	3583	13	0	0
T9	2657	5	0	0
T10	5838	0	0	0
T11	0	9	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	1301	0	0
T1	2876	9	0	0
T2	35282	0	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	1	0	0
T6	29248	0	0	0
T7	4208	0	0	0
T8	3583	13	0	0
T9	2657	1	0	0
T10	5838	0	0	0
T11	0	9	0	0
T41	0	3	0	0
T48	0	28	0	0
T86	0	18	0	0
T87	0	8	0	0
T88	0	8	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	15118	0	0
T1	2876	9	0	0
T2	35282	28	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	5	0	0
T6	29248	75	0	0
T7	4208	4	0	0
T8	3583	13	0	0
T9	2657	5	0	0
T10	5838	0	0	0
T11	0	9	0	0
T12	0	4	0	0
T13	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	1301	0	0
T1	2876	9	0	0
T2	35282	0	0	0
T3	5059	0	0	0
T4	3544	0	0	0
T5	2918	1	0	0
T6	29248	0	0	0
T7	4208	0	0	0
T8	3583	13	0	0
T9	2657	1	0	0
T10	5838	0	0	0
T11	0	9	0	0
T41	0	3	0	0
T48	0	28	0	0
T86	0	18	0	0
T87	0	8	0	0
T88	0	8	0	0