Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12683017	8168	0	0
alert_regwen_rd_A	12683017	4265	0	0
cpu_regwen_rd_A	12683017	4090	0	0
sw_rst_ctrl_n_0_rd_A	12683017	8109	0	0
sw_rst_ctrl_n_1_rd_A	12683017	8199	0	0
sw_rst_ctrl_n_2_rd_A	12683017	8158	0	0
sw_rst_ctrl_n_3_rd_A	12683017	8166	0	0
sw_rst_ctrl_n_4_rd_A	12683017	8213	0	0
sw_rst_ctrl_n_5_rd_A	12683017	8180	0	0
sw_rst_ctrl_n_6_rd_A	12683017	8333	0	0
sw_rst_ctrl_n_7_rd_A	12683017	7955	0	0
sw_rst_regwen_0_rd_A	12683017	4481	0	0
sw_rst_regwen_1_rd_A	12683017	4718	0	0
sw_rst_regwen_2_rd_A	12683017	4437	0	0
sw_rst_regwen_3_rd_A	12683017	4691	0	0
sw_rst_regwen_4_rd_A	12683017	4722	0	0
sw_rst_regwen_5_rd_A	12683017	4532	0	0
sw_rst_regwen_6_rd_A	12683017	4647	0	0
sw_rst_regwen_7_rd_A	12683017	4483	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	8168	0	0
T65	12713	632	0	0
T66	2148	16	0	0
T67	4533	24	0	0
T68	2624	95	0	0
T69	6536	303	0	0
T70	3164	26	0	0
T92	3635	36	0	0
T93	6772	262	0	0
T96	20634	3	0	0
T97	17753	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	4265	0	0
T2	30813	50	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T58	0	183	0	0
T101	0	144	0	0
T102	0	28	0	0
T104	0	79	0	0
T121	0	214	0	0
T122	0	179	0	0
T123	0	42	0	0
T124	0	90	0	0
T125	0	332	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	4090	0	0
T2	30813	51	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T58	0	148	0	0
T101	0	105	0	0
T102	0	41	0	0
T104	0	58	0	0
T121	0	265	0	0
T122	0	183	0	0
T123	0	18	0	0
T124	0	84	0	0
T125	0	343	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	8109	0	0
T2	30813	52	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	20	0	0
T45	0	37	0	0
T54	0	201	0	0
T58	0	726	0	0
T101	0	156	0	0
T104	0	77	0	0
T126	0	144	0	0
T127	0	50	0	0
T128	0	39	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	8199	0	0
T2	30813	49	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	12	0	0
T45	0	42	0	0
T54	0	195	0	0
T58	0	637	0	0
T101	0	150	0	0
T104	0	51	0	0
T126	0	164	0	0
T127	0	53	0	0
T128	0	64	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	8158	0	0
T2	30813	61	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	21	0	0
T45	0	38	0	0
T54	0	196	0	0
T58	0	723	0	0
T101	0	119	0	0
T104	0	59	0	0
T126	0	170	0	0
T127	0	48	0	0
T128	0	46	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	8166	0	0
T2	30813	54	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	12	0	0
T45	0	59	0	0
T54	0	199	0	0
T58	0	767	0	0
T101	0	163	0	0
T104	0	80	0	0
T126	0	152	0	0
T127	0	56	0	0
T128	0	64	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	8213	0	0
T2	30813	61	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	8	0	0
T45	0	26	0	0
T54	0	184	0	0
T58	0	758	0	0
T101	0	129	0	0
T104	0	77	0	0
T126	0	184	0	0
T127	0	37	0	0
T128	0	32	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	8180	0	0
T2	30813	50	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	20	0	0
T45	0	24	0	0
T54	0	228	0	0
T58	0	697	0	0
T101	0	154	0	0
T104	0	63	0	0
T126	0	172	0	0
T127	0	55	0	0
T128	0	52	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	8333	0	0
T2	30813	50	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	10	0	0
T45	0	34	0	0
T54	0	198	0	0
T58	0	712	0	0
T101	0	139	0	0
T104	0	64	0	0
T126	0	131	0	0
T127	0	42	0	0
T128	0	47	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	7955	0	0
T2	30813	49	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	7	0	0
T45	0	64	0	0
T54	0	211	0	0
T58	0	679	0	0
T101	0	161	0	0
T104	0	55	0	0
T126	0	168	0	0
T127	0	46	0	0
T128	0	72	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	4481	0	0
T2	30813	57	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	3	0	0
T54	0	23	0	0
T58	0	165	0	0
T59	0	9	0	0
T101	0	116	0	0
T102	0	29	0	0
T104	0	50	0	0
T126	0	37	0	0
T129	0	2	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	4718	0	0
T2	30813	36	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	5	0	0
T54	0	39	0	0
T58	0	175	0	0
T59	0	8	0	0
T101	0	129	0	0
T102	0	27	0	0
T104	0	67	0	0
T126	0	23	0	0
T129	0	5	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	4437	0	0
T2	30813	58	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	2	0	0
T54	0	32	0	0
T58	0	165	0	0
T59	0	7	0	0
T101	0	111	0	0
T102	0	26	0	0
T104	0	80	0	0
T126	0	18	0	0
T129	0	7	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	4691	0	0
T2	30813	60	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	9	0	0
T54	0	39	0	0
T58	0	187	0	0
T59	0	14	0	0
T101	0	137	0	0
T102	0	15	0	0
T104	0	62	0	0
T126	0	26	0	0
T129	0	7	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	4722	0	0
T2	30813	52	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	3	0	0
T54	0	36	0	0
T58	0	152	0	0
T59	0	12	0	0
T101	0	112	0	0
T102	0	22	0	0
T104	0	76	0	0
T126	0	33	0	0
T129	0	1	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	4532	0	0
T2	30813	44	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	16	0	0
T54	0	36	0	0
T58	0	172	0	0
T59	0	9	0	0
T101	0	112	0	0
T102	0	17	0	0
T104	0	46	0	0
T126	0	22	0	0
T129	0	3	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	4647	0	0
T2	30813	74	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	6	0	0
T54	0	37	0	0
T58	0	182	0	0
T59	0	3	0	0
T101	0	131	0	0
T102	0	23	0	0
T104	0	76	0	0
T126	0	35	0	0
T129	0	4	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12683017	4483	0	0
T2	30813	41	0	0
T3	4993	0	0	0
T4	3429	0	0	0
T5	2722	0	0	0
T6	26088	0	0	0
T7	3916	0	0	0
T8	3540	0	0	0
T9	2366	0	0	0
T10	5482	0	0	0
T11	2899	0	0	0
T13	0	1	0	0
T54	0	35	0	0
T58	0	167	0	0
T59	0	6	0	0
T101	0	123	0	0
T102	0	9	0	0
T104	0	73	0	0
T126	0	27	0	0
T129	0	7	0	0