Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T7
0	1	Covered	T2,T7,T9
1	0	Covered	T2,T5,T13

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T5,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55958958	9029	0	0
CascadeEffAonToRstPorAboveRise_A	55958958	9029	0	0
CascadeEffAonToRstPorIoAboveFall_A	53718484	9029	0	0
CascadeEffAonToRstPorIoAboveRise_A	53718484	9029	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26860412	9029	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26860412	9029	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13429862	9029	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13429862	9029	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26860317	9029	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26860317	9029	0	0
CascadeLcToLcAboveFall_A	55958958	22885	0	0
CascadeLcToLcAboveRise_A	55958958	22885	0	0
CascadeLcToLcAonAboveFall_A	1696633	22885	0	0
CascadeLcToLcAonAboveRise_A	1696633	22885	0	0
CascadeLcToLcShadowedAboveFall_A	55958958	22885	0	0
CascadeLcToLcShadowedAboveRise_A	55958958	22885	0	0
CascadePorToAonAboveFall_A	1696633	6890	0	0
CascadeSysToSysAboveFall_A	55958958	22885	0	0
CascadeSysToSysAboveRise_A	55958958	22885	0	0
ScanRstToAonRise_A	1696633	232	0	0
StablePorToAonRise_A	1696633	9029	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11831070	22885	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11831070	22885	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11831070	22885	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11831070	22885	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13429862	22885	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13429862	22885	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11831070	22885	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11831070	22885	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11831070	22885	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11831070	22885	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55958958	9029	0	0
T1	11985	1	0	0
T2	147006	16	0	0
T3	21084	2	0	0
T4	14768	2	0	0
T5	12161	2	0	0
T6	121892	27	0	0
T7	17535	2	0	0
T8	14931	1	0	0
T9	11069	2	0	0
T10	24316	8	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55958958	9029	0	0
T1	11985	1	0	0
T2	147006	16	0	0
T3	21084	2	0	0
T4	14768	2	0	0
T5	12161	2	0	0
T6	121892	27	0	0
T7	17535	2	0	0
T8	14931	1	0	0
T9	11069	2	0	0
T10	24316	8	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53718484	9029	0	0
T1	11504	1	0	0
T2	141111	16	0	0
T3	20240	2	0	0
T4	14177	2	0	0
T5	11669	2	0	0
T6	116956	27	0	0
T7	16832	2	0	0
T8	14332	1	0	0
T9	10628	2	0	0
T10	23347	8	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53718484	9029	0	0
T1	11504	1	0	0
T2	141111	16	0	0
T3	20240	2	0	0
T4	14177	2	0	0
T5	11669	2	0	0
T6	116956	27	0	0
T7	16832	2	0	0
T8	14332	1	0	0
T9	10628	2	0	0
T10	23347	8	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26860412	9029	0	0
T1	5753	1	0	0
T2	70551	16	0	0
T3	10120	2	0	0
T4	7088	2	0	0
T5	5833	2	0	0
T6	58495	27	0	0
T7	8418	2	0	0
T8	7166	1	0	0
T9	5315	2	0	0
T10	11675	8	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26860412	9029	0	0
T1	5753	1	0	0
T2	70551	16	0	0
T3	10120	2	0	0
T4	7088	2	0	0
T5	5833	2	0	0
T6	58495	27	0	0
T7	8418	2	0	0
T8	7166	1	0	0
T9	5315	2	0	0
T10	11675	8	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	9029	0	0
T1	2876	1	0	0
T2	35282	16	0	0
T3	5059	2	0	0
T4	3544	2	0	0
T5	2918	2	0	0
T6	29248	27	0	0
T7	4208	2	0	0
T8	3583	1	0	0
T9	2657	2	0	0
T10	5838	8	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	9029	0	0
T1	2876	1	0	0
T2	35282	16	0	0
T3	5059	2	0	0
T4	3544	2	0	0
T5	2918	2	0	0
T6	29248	27	0	0
T7	4208	2	0	0
T8	3583	1	0	0
T9	2657	2	0	0
T10	5838	8	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26860317	9029	0	0
T1	5752	1	0	0
T2	70553	16	0	0
T3	10120	2	0	0
T4	7088	2	0	0
T5	5835	2	0	0
T6	58486	27	0	0
T7	8413	2	0	0
T8	7166	1	0	0
T9	5315	2	0	0
T10	11672	8	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26860317	9029	0	0
T1	5752	1	0	0
T2	70553	16	0	0
T3	10120	2	0	0
T4	7088	2	0	0
T5	5835	2	0	0
T6	58486	27	0	0
T7	8413	2	0	0
T8	7166	1	0	0
T9	5315	2	0	0
T10	11672	8	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55958958	22885	0	0
T1	11985	1	0	0
T2	147006	44	0	0
T3	21084	2	0	0
T4	14768	2	0	0
T5	12161	6	0	0
T6	121892	102	0	0
T7	17535	6	0	0
T8	14931	1	0	0
T9	11069	6	0	0
T10	24316	8	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55958958	22885	0	0
T1	11985	1	0	0
T2	147006	44	0	0
T3	21084	2	0	0
T4	14768	2	0	0
T5	12161	6	0	0
T6	121892	102	0	0
T7	17535	6	0	0
T8	14931	1	0	0
T9	11069	6	0	0
T10	24316	8	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696633	22885	0	0
T1	357	1	0	0
T2	4458	44	0	0
T3	631	2	0	0
T4	443	2	0	0
T5	364	6	0	0
T6	3670	102	0	0
T7	524	6	0	0
T8	447	1	0	0
T9	332	6	0	0
T10	731	8	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696633	22885	0	0
T1	357	1	0	0
T2	4458	44	0	0
T3	631	2	0	0
T4	443	2	0	0
T5	364	6	0	0
T6	3670	102	0	0
T7	524	6	0	0
T8	447	1	0	0
T9	332	6	0	0
T10	731	8	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55958958	22885	0	0
T1	11985	1	0	0
T2	147006	44	0	0
T3	21084	2	0	0
T4	14768	2	0	0
T5	12161	6	0	0
T6	121892	102	0	0
T7	17535	6	0	0
T8	14931	1	0	0
T9	11069	6	0	0
T10	24316	8	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55958958	22885	0	0
T1	11985	1	0	0
T2	147006	44	0	0
T3	21084	2	0	0
T4	14768	2	0	0
T5	12161	6	0	0
T6	121892	102	0	0
T7	17535	6	0	0
T8	14931	1	0	0
T9	11069	6	0	0
T10	24316	8	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696633	6890	0	0
T1	357	1	0	0
T2	4458	6	0	0
T3	631	20	0	0
T4	443	8	0	0
T5	364	1	0	0
T6	3670	27	0	0
T7	524	1	0	0
T8	447	1	0	0
T9	332	1	0	0
T10	731	8	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55958958	22885	0	0
T1	11985	1	0	0
T2	147006	44	0	0
T3	21084	2	0	0
T4	14768	2	0	0
T5	12161	6	0	0
T6	121892	102	0	0
T7	17535	6	0	0
T8	14931	1	0	0
T9	11069	6	0	0
T10	24316	8	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55958958	22885	0	0
T1	11985	1	0	0
T2	147006	44	0	0
T3	21084	2	0	0
T4	14768	2	0	0
T5	12161	6	0	0
T6	121892	102	0	0
T7	17535	6	0	0
T8	14931	1	0	0
T9	11069	6	0	0
T10	24316	8	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696633	232	0	0
T9	332	1	0	0
T10	731	0	0	0
T11	373	0	0	0
T12	314	0	0	0
T13	746	0	0	0
T14	2732	2	0	0
T23	335	0	0	0
T25	729	0	0	0
T34	180	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T48	0	4	0	0
T85	732	0	0	0
T86	0	1	0	0
T90	0	7	0	0
T104	0	2	0	0
T131	0	4	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696633	9029	0	0
T1	357	1	0	0
T2	4458	16	0	0
T3	631	2	0	0
T4	443	2	0	0
T5	364	2	0	0
T6	3670	27	0	0
T7	524	2	0	0
T8	447	1	0	0
T9	332	2	0	0
T10	731	8	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11831070	22885	0	0
T1	2809	1	0	0
T2	30813	44	0	0
T3	4993	2	0	0
T4	3429	2	0	0
T5	2722	6	0	0
T6	26088	102	0	0
T7	3916	6	0	0
T8	3540	1	0	0
T9	2366	6	0	0
T10	5482	8	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11831070	22885	0	0
T1	2809	1	0	0
T2	30813	44	0	0
T3	4993	2	0	0
T4	3429	2	0	0
T5	2722	6	0	0
T6	26088	102	0	0
T7	3916	6	0	0
T8	3540	1	0	0
T9	2366	6	0	0
T10	5482	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11831070	22885	0	0
T1	2809	1	0	0
T2	30813	44	0	0
T3	4993	2	0	0
T4	3429	2	0	0
T5	2722	6	0	0
T6	26088	102	0	0
T7	3916	6	0	0
T8	3540	1	0	0
T9	2366	6	0	0
T10	5482	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11831070	22885	0	0
T1	2809	1	0	0
T2	30813	44	0	0
T3	4993	2	0	0
T4	3429	2	0	0
T5	2722	6	0	0
T6	26088	102	0	0
T7	3916	6	0	0
T8	3540	1	0	0
T9	2366	6	0	0
T10	5482	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	22885	0	0
T1	2876	1	0	0
T2	35282	44	0	0
T3	5059	2	0	0
T4	3544	2	0	0
T5	2918	6	0	0
T6	29248	102	0	0
T7	4208	6	0	0
T8	3583	1	0	0
T9	2657	6	0	0
T10	5838	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13429862	22885	0	0
T1	2876	1	0	0
T2	35282	44	0	0
T3	5059	2	0	0
T4	3544	2	0	0
T5	2918	6	0	0
T6	29248	102	0	0
T7	4208	6	0	0
T8	3583	1	0	0
T9	2657	6	0	0
T10	5838	8	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11831070	22885	0	0
T1	2809	1	0	0
T2	30813	44	0	0
T3	4993	2	0	0
T4	3429	2	0	0
T5	2722	6	0	0
T6	26088	102	0	0
T7	3916	6	0	0
T8	3540	1	0	0
T9	2366	6	0	0
T10	5482	8	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11831070	22885	0	0
T1	2809	1	0	0
T2	30813	44	0	0
T3	4993	2	0	0
T4	3429	2	0	0
T5	2722	6	0	0
T6	26088	102	0	0
T7	3916	6	0	0
T8	3540	1	0	0
T9	2366	6	0	0
T10	5482	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11831070	22885	0	0
T1	2809	1	0	0
T2	30813	44	0	0
T3	4993	2	0	0
T4	3429	2	0	0
T5	2722	6	0	0
T6	26088	102	0	0
T7	3916	6	0	0
T8	3540	1	0	0
T9	2366	6	0	0
T10	5482	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11831070	22885	0	0
T1	2809	1	0	0
T2	30813	44	0	0
T3	4993	2	0	0
T4	3429	2	0	0
T5	2722	6	0	0
T6	26088	102	0	0
T7	3916	6	0	0
T8	3540	1	0	0
T9	2366	6	0	0
T10	5482	8	0	0