Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	583266	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

350783

1

T2

376

T3

945

T4

3457

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	496504	1			T2	539		T3	1404		T4	5172
values[0x0]	218797	1			T2	246		T3	641		T4	2037
values[0x1]	218748	1			T2	247		T3	585		T4	2129

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	490055	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

443994

1

T2

486

T3

1195

T4

4372

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3531	1			T4	25		T5	8		T13	7
valid_sources[0x01]	5757	1			T4	37		T5	13		T14	7
valid_sources[0x02]	4381	1			T4	31		T5	6		T14	5
valid_sources[0x03]	3180	1			T4	32		T5	12		T14	8
valid_sources[0x04]	3577	1			T4	40		T5	7		T14	4
valid_sources[0x05]	4209	1			T2	9		T4	32		T5	12
valid_sources[0x06]	4124	1			T4	43		T5	13		T14	5
valid_sources[0x07]	3863	1			T4	31		T5	24		T9	1
valid_sources[0x08]	3021	1			T2	19		T4	34		T5	7
valid_sources[0x09]	3117	1			T4	27		T5	19		T14	2
valid_sources[0x0a]	3476	1			T4	38		T5	12		T13	3
valid_sources[0x0b]	3239	1			T4	42		T5	5		T13	7
valid_sources[0x0c]	6345	1			T2	4		T4	39		T5	21
valid_sources[0x0d]	3023	1			T4	38		T5	8		T14	9
valid_sources[0x0e]	3999	1			T2	2		T4	38		T5	15
valid_sources[0x0f]	3830	1			T2	9		T4	36		T5	31
valid_sources[0x10]	3603	1			T4	32		T5	17		T11	1
valid_sources[0x11]	3641	1			T3	13		T4	38		T5	3
valid_sources[0x12]	3930	1			T4	39		T5	20		T14	1
valid_sources[0x13]	3440	1			T2	6		T4	28		T5	3
valid_sources[0x14]	3931	1			T4	36		T5	10		T14	1
valid_sources[0x15]	3479	1			T4	41		T5	17		T14	3
valid_sources[0x16]	3443	1			T2	22		T4	36		T5	14
valid_sources[0x17]	4045	1			T2	13		T4	29		T5	17
valid_sources[0x18]	3550	1			T2	1		T4	45		T5	16
valid_sources[0x19]	3401	1			T4	29		T5	10		T14	6
valid_sources[0x1a]	3392	1			T4	43		T5	19		T14	1
valid_sources[0x1b]	3477	1			T4	40		T5	17		T14	4
valid_sources[0x1c]	3434	1			T4	26		T5	18		T14	9
valid_sources[0x1d]	3775	1			T4	37		T5	19		T14	4
valid_sources[0x1e]	3485	1			T4	32		T5	17		T14	1
valid_sources[0x1f]	3327	1			T4	37		T5	9		T14	6
valid_sources[0x20]	3151	1			T4	42		T5	12		T13	28
valid_sources[0x21]	2926	1			T4	36		T5	11		T14	5
valid_sources[0x22]	3261	1			T2	31		T4	30		T5	31
valid_sources[0x23]	3252	1			T2	10		T4	40		T5	13
valid_sources[0x24]	4211	1			T4	42		T5	16		T13	4
valid_sources[0x25]	3497	1			T4	29		T5	8		T14	8
valid_sources[0x26]	7569	1			T4	28		T5	7		T12	170
valid_sources[0x27]	6984	1			T4	39		T5	13		T14	4
valid_sources[0x28]	3720	1			T2	14		T4	30		T5	11
valid_sources[0x29]	3341	1			T2	24		T4	39		T5	8
valid_sources[0x2a]	3096	1			T4	34		T5	8		T13	5
valid_sources[0x2b]	3187	1			T4	40		T5	15		T14	4
valid_sources[0x2c]	2942	1			T4	37		T5	16		T14	4
valid_sources[0x2d]	3563	1			T2	24		T4	41		T5	8
valid_sources[0x2e]	3315	1			T4	45		T5	12		T27	3
valid_sources[0x2f]	3015	1			T4	42		T5	7		T14	5
valid_sources[0x30]	3652	1			T2	9		T4	38		T5	11
valid_sources[0x31]	3193	1			T2	3		T4	36		T5	19
valid_sources[0x32]	4580	1			T4	36		T5	19		T14	3
valid_sources[0x33]	3067	1			T4	32		T5	17		T14	2
valid_sources[0x34]	4723	1			T4	26		T5	34		T14	5
valid_sources[0x35]	3574	1			T4	29		T5	4		T13	6
valid_sources[0x36]	3157	1			T2	4		T4	39		T5	5
valid_sources[0x37]	3680	1			T4	27		T5	18		T14	7
valid_sources[0x38]	2982	1			T4	32		T5	20		T13	3
valid_sources[0x39]	3431	1			T2	14		T4	31		T5	24
valid_sources[0x3a]	3075	1			T2	12		T4	39		T5	23
valid_sources[0x3b]	4159	1			T4	37		T5	22		T14	2
valid_sources[0x3c]	3152	1			T4	44		T5	12		T14	9
valid_sources[0x3d]	3519	1			T2	11		T4	28		T5	5
valid_sources[0x3e]	3672	1			T3	3		T4	31		T5	16
valid_sources[0x3f]	4301	1			T4	37		T5	14		T14	2
valid_sources[0x40]	4181	1			T4	31		T5	6		T14	2
valid_sources[0x41]	3308	1			T4	43		T5	18		T14	6
valid_sources[0x42]	3087	1			T4	44		T5	13		T14	8
valid_sources[0x43]	4490	1			T4	41		T5	13		T14	1
valid_sources[0x44]	4235	1			T4	38		T5	13		T14	2
valid_sources[0x45]	3228	1			T4	41		T5	3		T14	2
valid_sources[0x46]	3060	1			T4	37		T5	29		T14	3
valid_sources[0x47]	2891	1			T2	12		T4	43		T5	1
valid_sources[0x48]	3227	1			T2	28		T4	23		T5	7
valid_sources[0x49]	2896	1			T4	36		T5	6		T14	7
valid_sources[0x4a]	3071	1			T4	26		T5	10		T13	1
valid_sources[0x4b]	3749	1			T2	13		T4	35		T5	16
valid_sources[0x4c]	3430	1			T2	14		T4	27		T5	10
valid_sources[0x4d]	3200	1			T4	28		T5	22		T14	5
valid_sources[0x4e]	3108	1			T4	37		T5	13		T13	13
valid_sources[0x4f]	3287	1			T2	20		T4	42		T5	7
valid_sources[0x50]	3660	1			T2	88		T3	185		T4	53
valid_sources[0x51]	3209	1			T2	5		T4	35		T5	11
valid_sources[0x52]	3223	1			T2	31		T4	38		T5	4
valid_sources[0x53]	3202	1			T2	15		T4	33		T5	11
valid_sources[0x54]	3518	1			T2	16		T4	39		T5	12
valid_sources[0x55]	3604	1			T2	3		T3	13		T4	38
valid_sources[0x56]	2964	1			T4	24		T5	10		T13	2
valid_sources[0x57]	2700	1			T2	1		T4	32		T5	13
valid_sources[0x58]	2949	1			T4	32		T5	5		T13	5
valid_sources[0x59]	3579	1			T4	30		T5	18		T14	5
valid_sources[0x5a]	3457	1			T4	40		T5	7		T14	2
valid_sources[0x5b]	3055	1			T2	26		T4	31		T5	27
valid_sources[0x5c]	3371	1			T2	13		T4	43		T5	16
valid_sources[0x5d]	2828	1			T4	31		T5	4		T14	5
valid_sources[0x5e]	3690	1			T2	9		T4	46		T5	7
valid_sources[0x5f]	4529	1			T4	37		T5	16		T14	5
valid_sources[0x60]	3554	1			T4	31		T5	9		T13	2
valid_sources[0x61]	2644	1			T4	32		T5	14		T13	3
valid_sources[0x62]	3401	1			T2	7		T4	43		T5	10
valid_sources[0x63]	3399	1			T4	35		T5	13		T13	8
valid_sources[0x64]	3120	1			T2	8		T4	41		T5	24
valid_sources[0x65]	3218	1			T2	4		T4	35		T5	8
valid_sources[0x66]	3157	1			T4	47		T5	16		T14	5
valid_sources[0x67]	3679	1			T4	36		T5	12		T14	6
valid_sources[0x68]	4015	1			T4	41		T5	10		T14	5
valid_sources[0x69]	2900	1			T4	33		T5	7		T14	3
valid_sources[0x6a]	3387	1			T4	33		T5	9		T14	4
valid_sources[0x6b]	3111	1			T2	11		T4	37		T5	7
valid_sources[0x6c]	3667	1			T4	29		T5	8		T14	2
valid_sources[0x6d]	3796	1			T4	37		T5	13		T14	3
valid_sources[0x6e]	3847	1			T4	44		T5	6		T14	5
valid_sources[0x6f]	3327	1			T4	33		T5	11		T14	7
valid_sources[0x70]	3045	1			T4	33		T5	15		T13	6
valid_sources[0x71]	2923	1			T4	51		T5	16		T14	6
valid_sources[0x72]	2722	1			T4	41		T5	19		T14	2
valid_sources[0x73]	3308	1			T2	10		T4	38		T5	13
valid_sources[0x74]	3618	1			T4	37		T5	15		T14	4
valid_sources[0x75]	3350	1			T4	51		T5	10		T14	3
valid_sources[0x76]	6206	1			T4	36		T5	20		T13	8
valid_sources[0x77]	2828	1			T4	43		T5	13		T14	2
valid_sources[0x78]	3085	1			T4	35		T5	12		T14	5
valid_sources[0x79]	3358	1			T4	36		T5	14		T14	4
valid_sources[0x7a]	3435	1			T4	26		T5	17		T13	7
valid_sources[0x7b]	3562	1			T4	39		T5	15		T14	6
valid_sources[0x7c]	3796	1			T2	3		T4	35		T5	14
valid_sources[0x7d]	7215	1			T2	10		T4	24		T5	15
valid_sources[0x7e]	3285	1			T2	52		T4	31		T5	13
valid_sources[0x7f]	3605	1			T4	31		T5	6		T14	5
valid_sources[0x80]	3934	1			T4	33		T5	16		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

233268

1

T2

249

T3

642

T4

2440

values[0x0]

all_enables

biggest_size

76361

1

T2

90

T3

194

T4

695

values[0x1]

all_enables

biggest_size

41154

1

T2

37

T3

109

T4

322