Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12884812	13316	0	0
gen_assertions[0].RstEnOn_A	12884812	961	0	0
gen_assertions[0].RstNOff_A	12884812	13316	0	0
gen_assertions[0].RstNOn_A	12884812	961	0	0
gen_assertions[1].RstEnOff_A	51538626	12127	0	0
gen_assertions[1].RstEnOn_A	51538626	916	0	0
gen_assertions[1].RstNOff_A	51538626	12127	0	0
gen_assertions[1].RstNOn_A	51538626	916	0	0
gen_assertions[2].RstEnOff_A	25770111	12164	0	0
gen_assertions[2].RstEnOn_A	25770111	903	0	0
gen_assertions[2].RstNOff_A	25770111	12164	0	0
gen_assertions[2].RstNOn_A	25770111	903	0	0
gen_assertions[3].RstEnOff_A	25770386	12252	0	0
gen_assertions[3].RstEnOn_A	25770386	982	0	0
gen_assertions[3].RstNOff_A	25770386	12252	0	0
gen_assertions[3].RstNOn_A	25770386	982	0	0
gen_assertions[4].RstEnOff_A	1626491	21345	0	0
gen_assertions[4].RstEnOn_A	1626491	1022	0	0
gen_assertions[4].RstNOff_A	1626491	21345	0	0
gen_assertions[4].RstNOn_A	1626491	1022	0	0
gen_assertions[5].RstEnOff_A	12884812	13579	0	0
gen_assertions[5].RstEnOn_A	12884812	1063	0	0
gen_assertions[5].RstNOff_A	12884812	13579	0	0
gen_assertions[5].RstNOn_A	12884812	1063	0	0
gen_assertions[6].RstEnOff_A	12884812	13642	0	0
gen_assertions[6].RstEnOn_A	12884812	1123	0	0
gen_assertions[6].RstNOff_A	12884812	13642	0	0
gen_assertions[6].RstNOn_A	12884812	1123	0	0
gen_assertions[7].RstEnOff_A	12884812	13665	0	0
gen_assertions[7].RstEnOn_A	12884812	1149	0	0
gen_assertions[7].RstNOff_A	12884812	13665	0	0
gen_assertions[7].RstNOn_A	12884812	1149	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	13316	0	0
T2	8433	6	0	0
T3	39444	42	0	0
T4	134713	123	0	0
T5	56441	75	0	0
T6	9952	3	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T12	0	11	0	0
T13	0	4	0	0
T14	0	4	0	0
T15	0	75	0	0
T16	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	961	0	0
T2	8433	6	0	0
T3	39444	0	0	0
T4	134713	8	0	0
T5	56441	0	0	0
T6	9952	3	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T12	0	6	0	0
T14	0	4	0	0
T16	0	1	0	0
T26	0	3	0	0
T63	0	1	0	0
T64	0	6	0	0
T66	0	7	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	13316	0	0
T2	8433	6	0	0
T3	39444	42	0	0
T4	134713	123	0	0
T5	56441	75	0	0
T6	9952	3	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T12	0	11	0	0
T13	0	4	0	0
T14	0	4	0	0
T15	0	75	0	0
T16	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	961	0	0
T2	8433	6	0	0
T3	39444	0	0	0
T4	134713	8	0	0
T5	56441	0	0	0
T6	9952	3	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T12	0	6	0	0
T14	0	4	0	0
T16	0	1	0	0
T26	0	3	0	0
T63	0	1	0	0
T64	0	6	0	0
T66	0	7	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51538626	12127	0	0
T2	33731	5	0	0
T3	157769	35	0	0
T4	538797	107	0	0
T5	225760	65	0	0
T6	39811	5	0	0
T7	23326	0	0	0
T8	19685	0	0	0
T9	5933	0	0	0
T10	23416	0	0	0
T11	8450	0	0	0
T12	0	7	0	0
T13	0	4	0	0
T14	0	8	0	0
T15	0	71	0	0
T16	0	5	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51538626	916	0	0
T2	33731	5	0	0
T3	157769	0	0	0
T4	538797	9	0	0
T5	225760	0	0	0
T6	39811	5	0	0
T7	23326	0	0	0
T8	19685	0	0	0
T9	5933	0	0	0
T10	23416	0	0	0
T11	8450	0	0	0
T12	0	2	0	0
T14	0	8	0	0
T16	0	1	0	0
T64	0	8	0	0
T66	0	8	0	0
T89	0	4	0	0
T90	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51538626	12127	0	0
T2	33731	5	0	0
T3	157769	35	0	0
T4	538797	107	0	0
T5	225760	65	0	0
T6	39811	5	0	0
T7	23326	0	0	0
T8	19685	0	0	0
T9	5933	0	0	0
T10	23416	0	0	0
T11	8450	0	0	0
T12	0	7	0	0
T13	0	4	0	0
T14	0	8	0	0
T15	0	71	0	0
T16	0	5	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51538626	916	0	0
T2	33731	5	0	0
T3	157769	0	0	0
T4	538797	9	0	0
T5	225760	0	0	0
T6	39811	5	0	0
T7	23326	0	0	0
T8	19685	0	0	0
T9	5933	0	0	0
T10	23416	0	0	0
T11	8450	0	0	0
T12	0	2	0	0
T14	0	8	0	0
T16	0	1	0	0
T64	0	8	0	0
T66	0	8	0	0
T89	0	4	0	0
T90	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25770111	12164	0	0
T2	16866	8	0	0
T3	78885	35	0	0
T4	269424	107	0	0
T5	112892	65	0	0
T6	19906	5	0	0
T7	11663	0	0	0
T8	9843	0	0	0
T9	2966	0	0	0
T10	11703	0	0	0
T11	4224	0	0	0
T12	0	7	0	0
T13	0	4	0	0
T14	0	7	0	0
T15	0	71	0	0
T16	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25770111	903	0	0
T2	16866	8	0	0
T3	78885	0	0	0
T4	269424	9	0	0
T5	112892	0	0	0
T6	19906	5	0	0
T7	11663	0	0	0
T8	9843	0	0	0
T9	2966	0	0	0
T10	11703	0	0	0
T11	4224	0	0	0
T14	0	7	0	0
T51	0	18	0	0
T64	0	10	0	0
T66	0	7	0	0
T89	0	5	0	0
T91	0	1	0	0
T92	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25770111	12164	0	0
T2	16866	8	0	0
T3	78885	35	0	0
T4	269424	107	0	0
T5	112892	65	0	0
T6	19906	5	0	0
T7	11663	0	0	0
T8	9843	0	0	0
T9	2966	0	0	0
T10	11703	0	0	0
T11	4224	0	0	0
T12	0	7	0	0
T13	0	4	0	0
T14	0	7	0	0
T15	0	71	0	0
T16	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25770111	903	0	0
T2	16866	8	0	0
T3	78885	0	0	0
T4	269424	9	0	0
T5	112892	0	0	0
T6	19906	5	0	0
T7	11663	0	0	0
T8	9843	0	0	0
T9	2966	0	0	0
T10	11703	0	0	0
T11	4224	0	0	0
T14	0	7	0	0
T51	0	18	0	0
T64	0	10	0	0
T66	0	7	0	0
T89	0	5	0	0
T91	0	1	0	0
T92	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25770386	12252	0	0
T2	16865	9	0	0
T3	78883	35	0	0
T4	269425	110	0	0
T5	112882	65	0	0
T6	19905	6	0	0
T7	11670	0	0	0
T8	9843	0	0	0
T9	2966	0	0	0
T10	11706	0	0	0
T11	4225	0	0	0
T12	0	7	0	0
T13	0	5	0	0
T14	0	11	0	0
T15	0	71	0	0
T16	0	5	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25770386	982	0	0
T2	16865	9	0	0
T3	78883	0	0	0
T4	269425	12	0	0
T5	112882	0	0	0
T6	19905	6	0	0
T7	11670	0	0	0
T8	9843	0	0	0
T9	2966	0	0	0
T10	11706	0	0	0
T11	4225	0	0	0
T13	0	1	0	0
T14	0	11	0	0
T16	0	1	0	0
T51	0	17	0	0
T64	0	9	0	0
T66	0	8	0	0
T89	0	5	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25770386	12252	0	0
T2	16865	9	0	0
T3	78883	35	0	0
T4	269425	110	0	0
T5	112882	65	0	0
T6	19905	6	0	0
T7	11670	0	0	0
T8	9843	0	0	0
T9	2966	0	0	0
T10	11706	0	0	0
T11	4225	0	0	0
T12	0	7	0	0
T13	0	5	0	0
T14	0	11	0	0
T15	0	71	0	0
T16	0	5	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25770386	982	0	0
T2	16865	9	0	0
T3	78883	0	0	0
T4	269425	12	0	0
T5	112882	0	0	0
T6	19905	6	0	0
T7	11670	0	0	0
T8	9843	0	0	0
T9	2966	0	0	0
T10	11706	0	0	0
T11	4225	0	0	0
T13	0	1	0	0
T14	0	11	0	0
T16	0	1	0	0
T51	0	17	0	0
T64	0	9	0	0
T66	0	8	0	0
T89	0	5	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626491	21345	0	0
T1	735	3	0	0
T2	1053	12	0	0
T3	5020	53	0	0
T4	17091	185	0	0
T5	7068	101	0	0
T6	1243	8	0	0
T7	731	2	0	0
T8	613	2	0	0
T9	184	1	0	0
T10	734	3	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626491	1022	0	0
T2	1053	11	0	0
T3	5020	0	0	0
T4	17091	13	0	0
T5	7068	0	0	0
T6	1243	7	0	0
T7	731	0	0	0
T8	613	0	0	0
T9	184	0	0	0
T10	734	0	0	0
T11	263	0	0	0
T13	0	1	0	0
T14	0	12	0	0
T51	0	21	0	0
T64	0	10	0	0
T66	0	10	0	0
T89	0	6	0	0
T93	0	5	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626491	21345	0	0
T1	735	3	0	0
T2	1053	12	0	0
T3	5020	53	0	0
T4	17091	185	0	0
T5	7068	101	0	0
T6	1243	8	0	0
T7	731	2	0	0
T8	613	2	0	0
T9	184	1	0	0
T10	734	3	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626491	1022	0	0
T2	1053	11	0	0
T3	5020	0	0	0
T4	17091	13	0	0
T5	7068	0	0	0
T6	1243	7	0	0
T7	731	0	0	0
T8	613	0	0	0
T9	184	0	0	0
T10	734	0	0	0
T11	263	0	0	0
T13	0	1	0	0
T14	0	12	0	0
T51	0	21	0	0
T64	0	10	0	0
T66	0	10	0	0
T89	0	6	0	0
T93	0	5	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	13579	0	0
T2	8433	12	0	0
T3	39444	42	0	0
T4	134713	126	0	0
T5	56441	75	0	0
T6	9952	7	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T12	0	11	0	0
T13	0	4	0	0
T14	0	10	0	0
T15	0	75	0	0
T16	0	5	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	1063	0	0
T2	8433	12	0	0
T3	39444	0	0	0
T4	134713	12	0	0
T5	56441	0	0	0
T6	9952	7	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T14	0	10	0	0
T16	0	1	0	0
T51	0	23	0	0
T64	0	12	0	0
T66	0	10	0	0
T89	0	8	0	0
T93	0	7	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	13579	0	0
T2	8433	12	0	0
T3	39444	42	0	0
T4	134713	126	0	0
T5	56441	75	0	0
T6	9952	7	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T12	0	11	0	0
T13	0	4	0	0
T14	0	10	0	0
T15	0	75	0	0
T16	0	5	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	1063	0	0
T2	8433	12	0	0
T3	39444	0	0	0
T4	134713	12	0	0
T5	56441	0	0	0
T6	9952	7	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T14	0	10	0	0
T16	0	1	0	0
T51	0	23	0	0
T64	0	12	0	0
T66	0	10	0	0
T89	0	8	0	0
T93	0	7	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	13642	0	0
T2	8433	10	0	0
T3	39444	42	0	0
T4	134713	128	0	0
T5	56441	75	0	0
T6	9952	9	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T12	0	11	0	0
T13	0	4	0	0
T14	0	14	0	0
T15	0	75	0	0
T16	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	1123	0	0
T2	8433	10	0	0
T3	39444	0	0	0
T4	134713	13	0	0
T5	56441	0	0	0
T6	9952	9	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T14	0	14	0	0
T51	0	20	0	0
T64	0	13	0	0
T66	0	12	0	0
T89	0	9	0	0
T91	0	1	0	0
T93	0	8	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	13642	0	0
T2	8433	10	0	0
T3	39444	42	0	0
T4	134713	128	0	0
T5	56441	75	0	0
T6	9952	9	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T12	0	11	0	0
T13	0	4	0	0
T14	0	14	0	0
T15	0	75	0	0
T16	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	1123	0	0
T2	8433	10	0	0
T3	39444	0	0	0
T4	134713	13	0	0
T5	56441	0	0	0
T6	9952	9	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T14	0	14	0	0
T51	0	20	0	0
T64	0	13	0	0
T66	0	12	0	0
T89	0	9	0	0
T91	0	1	0	0
T93	0	8	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	13665	0	0
T2	8433	14	0	0
T3	39444	42	0	0
T4	134713	126	0	0
T5	56441	75	0	0
T6	9952	11	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T12	0	11	0	0
T13	0	4	0	0
T14	0	15	0	0
T15	0	75	0	0
T16	0	5	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	1149	0	0
T2	8433	14	0	0
T3	39444	0	0	0
T4	134713	11	0	0
T5	56441	0	0	0
T6	9952	11	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T14	0	15	0	0
T16	0	1	0	0
T51	0	22	0	0
T64	0	13	0	0
T66	0	14	0	0
T89	0	9	0	0
T93	0	9	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	13665	0	0
T2	8433	14	0	0
T3	39444	42	0	0
T4	134713	126	0	0
T5	56441	75	0	0
T6	9952	11	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T12	0	11	0	0
T13	0	4	0	0
T14	0	15	0	0
T15	0	75	0	0
T16	0	5	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	1149	0	0
T2	8433	14	0	0
T3	39444	0	0	0
T4	134713	11	0	0
T5	56441	0	0	0
T6	9952	11	0	0
T7	5831	0	0	0
T8	4920	0	0	0
T9	1483	0	0	0
T10	5851	0	0	0
T11	2112	0	0	0
T14	0	15	0	0
T16	0	1	0	0
T51	0	22	0	0
T64	0	13	0	0
T66	0	14	0	0
T89	0	9	0	0
T93	0	9	0	0