Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12320802	7667	0	0
alert_regwen_rd_A	12320802	4972	0	0
cpu_regwen_rd_A	12320802	4827	0	0
sw_rst_ctrl_n_0_rd_A	12320802	8291	0	0
sw_rst_ctrl_n_1_rd_A	12320802	8817	0	0
sw_rst_ctrl_n_2_rd_A	12320802	8773	0	0
sw_rst_ctrl_n_3_rd_A	12320802	8325	0	0
sw_rst_ctrl_n_4_rd_A	12320802	8480	0	0
sw_rst_ctrl_n_5_rd_A	12320802	8713	0	0
sw_rst_ctrl_n_6_rd_A	12320802	8729	0	0
sw_rst_ctrl_n_7_rd_A	12320802	8409	0	0
sw_rst_regwen_0_rd_A	12320802	5373	0	0
sw_rst_regwen_1_rd_A	12320802	5696	0	0
sw_rst_regwen_2_rd_A	12320802	5655	0	0
sw_rst_regwen_3_rd_A	12320802	5543	0	0
sw_rst_regwen_4_rd_A	12320802	5514	0	0
sw_rst_regwen_5_rd_A	12320802	5513	0	0
sw_rst_regwen_6_rd_A	12320802	5507	0	0
sw_rst_regwen_7_rd_A	12320802	5592	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	7667	0	0
T72	4619	221	0	0
T73	17469	4	0	0
T74	2373	3	0	0
T75	2287	194	0	0
T97	2466	85	0	0
T98	2709	197	0	0
T99	11873	3	0	0
T100	5159	238	0	0
T103	11597	2	0	0
T104	20994	3	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	4972	0	0
T3	35357	47	0	0
T4	120640	106	0	0
T5	53203	0	0	0
T6	9909	0	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	75	0	0
T54	0	13	0	0
T83	0	52	0	0
T87	0	86	0	0
T107	0	49	0	0
T113	0	39	0	0
T114	0	42	0	0
T136	0	650	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	4827	0	0
T3	35357	50	0	0
T4	120640	93	0	0
T5	53203	0	0	0
T6	9909	0	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	71	0	0
T54	0	16	0	0
T83	0	67	0	0
T87	0	91	0	0
T107	0	54	0	0
T113	0	43	0	0
T114	0	52	0	0
T136	0	617	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	8291	0	0
T3	35357	55	0	0
T4	120640	192	0	0
T5	53203	0	0	0
T6	9909	158	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	275	0	0
T52	0	30	0	0
T54	0	27	0	0
T64	0	100	0	0
T66	0	172	0	0
T89	0	91	0	0
T93	0	119	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	8817	0	0
T3	35357	49	0	0
T4	120640	177	0	0
T5	53203	0	0	0
T6	9909	147	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	282	0	0
T52	0	23	0	0
T54	0	26	0	0
T64	0	135	0	0
T66	0	180	0	0
T89	0	83	0	0
T93	0	163	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	8773	0	0
T3	35357	34	0	0
T4	120640	224	0	0
T5	53203	0	0	0
T6	9909	134	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	228	0	0
T52	0	33	0	0
T54	0	25	0	0
T64	0	143	0	0
T66	0	212	0	0
T89	0	125	0	0
T93	0	113	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	8325	0	0
T3	35357	43	0	0
T4	120640	173	0	0
T5	53203	0	0	0
T6	9909	169	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	198	0	0
T52	0	32	0	0
T54	0	14	0	0
T64	0	86	0	0
T66	0	178	0	0
T89	0	93	0	0
T93	0	136	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	8480	0	0
T3	35357	32	0	0
T4	120640	184	0	0
T5	53203	0	0	0
T6	9909	148	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	232	0	0
T52	0	29	0	0
T54	0	19	0	0
T64	0	105	0	0
T66	0	217	0	0
T89	0	65	0	0
T93	0	131	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	8713	0	0
T3	35357	34	0	0
T4	120640	208	0	0
T5	53203	0	0	0
T6	9909	125	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	241	0	0
T52	0	33	0	0
T54	0	21	0	0
T64	0	134	0	0
T66	0	192	0	0
T89	0	79	0	0
T93	0	140	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	8729	0	0
T3	35357	37	0	0
T4	120640	179	0	0
T5	53203	0	0	0
T6	9909	183	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	224	0	0
T52	0	29	0	0
T54	0	22	0	0
T64	0	142	0	0
T66	0	233	0	0
T89	0	118	0	0
T93	0	97	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	8409	0	0
T3	35357	32	0	0
T4	120640	212	0	0
T5	53203	0	0	0
T6	9909	121	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	197	0	0
T52	0	30	0	0
T54	0	36	0	0
T64	0	126	0	0
T66	0	180	0	0
T89	0	83	0	0
T93	0	142	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	5373	0	0
T3	35357	49	0	0
T4	120640	91	0	0
T5	53203	0	0	0
T6	9909	34	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	80	0	0
T54	0	46	0	0
T64	0	25	0	0
T66	0	27	0	0
T89	0	16	0	0
T93	0	53	0	0
T107	0	62	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	5696	0	0
T3	35357	55	0	0
T4	120640	135	0	0
T5	53203	0	0	0
T6	9909	38	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	114	0	0
T54	0	30	0	0
T64	0	23	0	0
T66	0	13	0	0
T89	0	10	0	0
T93	0	22	0	0
T107	0	51	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	5655	0	0
T3	35357	45	0	0
T4	120640	96	0	0
T5	53203	0	0	0
T6	9909	29	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	68	0	0
T54	0	34	0	0
T64	0	5	0	0
T66	0	38	0	0
T89	0	6	0	0
T93	0	49	0	0
T107	0	37	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	5543	0	0
T3	35357	57	0	0
T4	120640	95	0	0
T5	53203	0	0	0
T6	9909	29	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	76	0	0
T54	0	53	0	0
T64	0	26	0	0
T66	0	38	0	0
T89	0	36	0	0
T93	0	28	0	0
T107	0	42	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	5514	0	0
T3	35357	44	0	0
T4	120640	95	0	0
T5	53203	0	0	0
T6	9909	17	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	103	0	0
T54	0	14	0	0
T64	0	13	0	0
T66	0	28	0	0
T89	0	13	0	0
T93	0	38	0	0
T107	0	33	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	5513	0	0
T3	35357	33	0	0
T4	120640	71	0	0
T5	53203	0	0	0
T6	9909	23	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	65	0	0
T54	0	14	0	0
T64	0	24	0	0
T66	0	28	0	0
T89	0	43	0	0
T93	0	40	0	0
T107	0	44	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	5507	0	0
T3	35357	51	0	0
T4	120640	75	0	0
T5	53203	0	0	0
T6	9909	17	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	71	0	0
T54	0	30	0	0
T64	0	16	0	0
T66	0	21	0	0
T89	0	5	0	0
T93	0	26	0	0
T107	0	51	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12320802	5592	0	0
T3	35357	48	0	0
T4	120640	101	0	0
T5	53203	0	0	0
T6	9909	35	0	0
T7	5286	0	0	0
T8	4830	0	0	0
T9	1440	0	0	0
T10	5499	0	0	0
T11	2045	0	0	0
T12	2326	0	0	0
T51	0	49	0	0
T54	0	30	0	0
T64	0	17	0	0
T66	0	35	0	0
T89	0	16	0	0
T93	0	30	0	0
T107	0	48	0	0