Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T13
0	1	Covered	T3,T4,T16
1	0	Covered	T3,T4,T13

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T4,T13
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	53687514	9009	0	0
CascadeEffAonToRstPorAboveRise_A	53687514	9009	0	0
CascadeEffAonToRstPorIoAboveFall_A	51538626	9009	0	0
CascadeEffAonToRstPorIoAboveRise_A	51538626	9009	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25770111	9009	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25770111	9009	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12884812	9009	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12884812	9009	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25770386	9009	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25770386	9009	0	0
CascadeLcToLcAboveFall_A	53687514	21554	0	0
CascadeLcToLcAboveRise_A	53687514	21554	0	0
CascadeLcToLcAonAboveFall_A	1626491	21554	0	0
CascadeLcToLcAonAboveRise_A	1626491	21554	0	0
CascadeLcToLcShadowedAboveFall_A	53687514	21554	0	0
CascadeLcToLcShadowedAboveRise_A	53687514	21554	0	0
CascadePorToAonAboveFall_A	1626491	7489	0	0
CascadeSysToSysAboveFall_A	53687514	21554	0	0
CascadeSysToSysAboveRise_A	53687514	21554	0	0
ScanRstToAonRise_A	1626491	189	0	0
StablePorToAonRise_A	1626491	9009	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11470905	21554	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11470905	21554	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11470905	21554	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11470905	21554	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12884812	21554	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12884812	21554	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11470905	21554	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11470905	21554	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11470905	21554	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11470905	21554	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53687514	9009	0	0
T1	24418	8	0	0
T2	35137	1	0	0
T3	164359	13	0	0
T4	561257	59	0	0
T5	235167	27	0	0
T6	41470	1	0	0
T7	24301	8	0	0
T8	20506	2	0	0
T9	6179	1	0	0
T10	24383	8	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53687514	9009	0	0
T1	24418	8	0	0
T2	35137	1	0	0
T3	164359	13	0	0
T4	561257	59	0	0
T5	235167	27	0	0
T6	41470	1	0	0
T7	24301	8	0	0
T8	20506	2	0	0
T9	6179	1	0	0
T10	24383	8	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51538626	9009	0	0
T1	23441	8	0	0
T2	33731	1	0	0
T3	157769	13	0	0
T4	538797	59	0	0
T5	225760	27	0	0
T6	39811	1	0	0
T7	23326	8	0	0
T8	19685	2	0	0
T9	5933	1	0	0
T10	23416	8	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51538626	9009	0	0
T1	23441	8	0	0
T2	33731	1	0	0
T3	157769	13	0	0
T4	538797	59	0	0
T5	225760	27	0	0
T6	39811	1	0	0
T7	23326	8	0	0
T8	19685	2	0	0
T9	5933	1	0	0
T10	23416	8	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25770111	9009	0	0
T1	11722	8	0	0
T2	16866	1	0	0
T3	78885	13	0	0
T4	269424	59	0	0
T5	112892	27	0	0
T6	19906	1	0	0
T7	11663	8	0	0
T8	9843	2	0	0
T9	2966	1	0	0
T10	11703	8	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25770111	9009	0	0
T1	11722	8	0	0
T2	16866	1	0	0
T3	78885	13	0	0
T4	269424	59	0	0
T5	112892	27	0	0
T6	19906	1	0	0
T7	11663	8	0	0
T8	9843	2	0	0
T9	2966	1	0	0
T10	11703	8	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	9009	0	0
T1	5860	8	0	0
T2	8433	1	0	0
T3	39444	13	0	0
T4	134713	59	0	0
T5	56441	27	0	0
T6	9952	1	0	0
T7	5831	8	0	0
T8	4920	2	0	0
T9	1483	1	0	0
T10	5851	8	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	9009	0	0
T1	5860	8	0	0
T2	8433	1	0	0
T3	39444	13	0	0
T4	134713	59	0	0
T5	56441	27	0	0
T6	9952	1	0	0
T7	5831	8	0	0
T8	4920	2	0	0
T9	1483	1	0	0
T10	5851	8	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25770386	9009	0	0
T1	11721	8	0	0
T2	16865	1	0	0
T3	78883	13	0	0
T4	269425	59	0	0
T5	112882	27	0	0
T6	19905	1	0	0
T7	11670	8	0	0
T8	9843	2	0	0
T9	2966	1	0	0
T10	11706	8	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25770386	9009	0	0
T1	11721	8	0	0
T2	16865	1	0	0
T3	78883	13	0	0
T4	269425	59	0	0
T5	112882	27	0	0
T6	19905	1	0	0
T7	11670	8	0	0
T8	9843	2	0	0
T9	2966	1	0	0
T10	11706	8	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53687514	21554	0	0
T1	24418	8	0	0
T2	35137	1	0	0
T3	164359	55	0	0
T4	561257	174	0	0
T5	235167	102	0	0
T6	41470	1	0	0
T7	24301	8	0	0
T8	20506	2	0	0
T9	6179	1	0	0
T10	24383	8	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53687514	21554	0	0
T1	24418	8	0	0
T2	35137	1	0	0
T3	164359	55	0	0
T4	561257	174	0	0
T5	235167	102	0	0
T6	41470	1	0	0
T7	24301	8	0	0
T8	20506	2	0	0
T9	6179	1	0	0
T10	24383	8	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626491	21554	0	0
T1	735	8	0	0
T2	1053	1	0	0
T3	5020	55	0	0
T4	17091	174	0	0
T5	7068	102	0	0
T6	1243	1	0	0
T7	731	8	0	0
T8	613	2	0	0
T9	184	1	0	0
T10	734	8	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626491	21554	0	0
T1	735	8	0	0
T2	1053	1	0	0
T3	5020	55	0	0
T4	17091	174	0	0
T5	7068	102	0	0
T6	1243	1	0	0
T7	731	8	0	0
T8	613	2	0	0
T9	184	1	0	0
T10	734	8	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53687514	21554	0	0
T1	24418	8	0	0
T2	35137	1	0	0
T3	164359	55	0	0
T4	561257	174	0	0
T5	235167	102	0	0
T6	41470	1	0	0
T7	24301	8	0	0
T8	20506	2	0	0
T9	6179	1	0	0
T10	24383	8	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53687514	21554	0	0
T1	24418	8	0	0
T2	35137	1	0	0
T3	164359	55	0	0
T4	561257	174	0	0
T5	235167	102	0	0
T6	41470	1	0	0
T7	24301	8	0	0
T8	20506	2	0	0
T9	6179	1	0	0
T10	24383	8	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626491	7489	0	0
T1	735	8	0	0
T2	1053	1	0	0
T3	5020	6	0	0
T4	17091	40	0	0
T5	7068	27	0	0
T6	1243	1	0	0
T7	731	8	0	0
T8	613	21	0	0
T9	184	1	0	0
T10	734	8	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53687514	21554	0	0
T1	24418	8	0	0
T2	35137	1	0	0
T3	164359	55	0	0
T4	561257	174	0	0
T5	235167	102	0	0
T6	41470	1	0	0
T7	24301	8	0	0
T8	20506	2	0	0
T9	6179	1	0	0
T10	24383	8	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53687514	21554	0	0
T1	24418	8	0	0
T2	35137	1	0	0
T3	164359	55	0	0
T4	561257	174	0	0
T5	235167	102	0	0
T6	41470	1	0	0
T7	24301	8	0	0
T8	20506	2	0	0
T9	6179	1	0	0
T10	24383	8	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626491	189	0	0
T3	5020	2	0	0
T4	17091	0	0	0
T5	7068	0	0	0
T6	1243	0	0	0
T7	731	0	0	0
T8	613	0	0	0
T9	184	0	0	0
T10	734	0	0	0
T11	263	0	0	0
T12	382	0	0	0
T51	0	2	0	0
T57	0	1	0	0
T94	0	2	0	0
T95	0	8	0	0
T111	0	7	0	0
T112	0	2	0	0
T113	0	1	0	0
T137	0	1	0	0
T138	0	5	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1626491	9009	0	0
T1	735	8	0	0
T2	1053	1	0	0
T3	5020	13	0	0
T4	17091	59	0	0
T5	7068	27	0	0
T6	1243	1	0	0
T7	731	8	0	0
T8	613	2	0	0
T9	184	1	0	0
T10	734	8	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11470905	21554	0	0
T1	5122	8	0	0
T2	8342	1	0	0
T3	35357	55	0	0
T4	120640	174	0	0
T5	53203	102	0	0
T6	9909	1	0	0
T7	5286	8	0	0
T8	4830	2	0	0
T9	1440	1	0	0
T10	5499	8	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11470905	21554	0	0
T1	5122	8	0	0
T2	8342	1	0	0
T3	35357	55	0	0
T4	120640	174	0	0
T5	53203	102	0	0
T6	9909	1	0	0
T7	5286	8	0	0
T8	4830	2	0	0
T9	1440	1	0	0
T10	5499	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11470905	21554	0	0
T1	5122	8	0	0
T2	8342	1	0	0
T3	35357	55	0	0
T4	120640	174	0	0
T5	53203	102	0	0
T6	9909	1	0	0
T7	5286	8	0	0
T8	4830	2	0	0
T9	1440	1	0	0
T10	5499	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11470905	21554	0	0
T1	5122	8	0	0
T2	8342	1	0	0
T3	35357	55	0	0
T4	120640	174	0	0
T5	53203	102	0	0
T6	9909	1	0	0
T7	5286	8	0	0
T8	4830	2	0	0
T9	1440	1	0	0
T10	5499	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	21554	0	0
T1	5860	8	0	0
T2	8433	1	0	0
T3	39444	55	0	0
T4	134713	174	0	0
T5	56441	102	0	0
T6	9952	1	0	0
T7	5831	8	0	0
T8	4920	2	0	0
T9	1483	1	0	0
T10	5851	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12884812	21554	0	0
T1	5860	8	0	0
T2	8433	1	0	0
T3	39444	55	0	0
T4	134713	174	0	0
T5	56441	102	0	0
T6	9952	1	0	0
T7	5831	8	0	0
T8	4920	2	0	0
T9	1483	1	0	0
T10	5851	8	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11470905	21554	0	0
T1	5122	8	0	0
T2	8342	1	0	0
T3	35357	55	0	0
T4	120640	174	0	0
T5	53203	102	0	0
T6	9909	1	0	0
T7	5286	8	0	0
T8	4830	2	0	0
T9	1440	1	0	0
T10	5499	8	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11470905	21554	0	0
T1	5122	8	0	0
T2	8342	1	0	0
T3	35357	55	0	0
T4	120640	174	0	0
T5	53203	102	0	0
T6	9909	1	0	0
T7	5286	8	0	0
T8	4830	2	0	0
T9	1440	1	0	0
T10	5499	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11470905	21554	0	0
T1	5122	8	0	0
T2	8342	1	0	0
T3	35357	55	0	0
T4	120640	174	0	0
T5	53203	102	0	0
T6	9909	1	0	0
T7	5286	8	0	0
T8	4830	2	0	0
T9	1440	1	0	0
T10	5499	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11470905	21554	0	0
T1	5122	8	0	0
T2	8342	1	0	0
T3	35357	55	0	0
T4	120640	174	0	0
T5	53203	102	0	0
T6	9909	1	0	0
T7	5286	8	0	0
T8	4830	2	0	0
T9	1440	1	0	0
T10	5499	8	0	0