Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	641756	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

385252

1

T2

10

T3

299

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	548670	1			T3	419		T6	571		T7	419
values[0x0]	239043	1			T2	13		T3	184		T4	2
values[0x1]	239295	1			T2	11		T3	189		T4	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	538918	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

488090

1

T2

12

T3

381

T4

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7124	1			T3	3		T6	4		T7	6
valid_sources[0x01]	3923	1			T6	5		T7	9		T8	1
valid_sources[0x02]	4004	1			T3	2		T15	7		T16	8
valid_sources[0x03]	3296	1			T3	3		T7	1		T8	3
valid_sources[0x04]	3999	1			T3	4		T6	4		T8	3
valid_sources[0x05]	4475	1			T3	4		T6	5		T8	1
valid_sources[0x06]	2990	1			T2	1		T6	2		T7	5
valid_sources[0x07]	3898	1			T6	5		T7	7		T15	10
valid_sources[0x08]	4852	1			T3	5		T6	1		T15	9
valid_sources[0x09]	4273	1			T3	2		T6	4		T7	13
valid_sources[0x0a]	3347	1			T6	6		T7	4		T15	2
valid_sources[0x0b]	4437	1			T3	2		T6	5		T7	3
valid_sources[0x0c]	3375	1			T3	4		T6	2		T8	2
valid_sources[0x0d]	3497	1			T2	1		T3	4		T6	7
valid_sources[0x0e]	3737	1			T3	7		T6	2		T7	1
valid_sources[0x0f]	4215	1			T3	3		T6	8		T8	9
valid_sources[0x10]	2900	1			T3	1		T6	10		T8	3
valid_sources[0x11]	3419	1			T3	5		T6	7		T7	2
valid_sources[0x12]	3779	1			T2	1		T3	2		T6	5
valid_sources[0x13]	4877	1			T3	3		T6	6		T7	6
valid_sources[0x14]	3982	1			T3	1		T6	2		T7	2
valid_sources[0x15]	4025	1			T6	7		T7	5		T9	1
valid_sources[0x16]	3671	1			T3	2		T6	6		T8	9
valid_sources[0x17]	3326	1			T3	7		T6	3		T7	1
valid_sources[0x18]	3307	1			T6	9		T7	2		T8	2
valid_sources[0x19]	3317	1			T3	1		T8	2		T15	14
valid_sources[0x1a]	3404	1			T3	5		T6	7		T7	4
valid_sources[0x1b]	3330	1			T3	4		T6	1		T15	5
valid_sources[0x1c]	3752	1			T3	5		T8	4		T15	3
valid_sources[0x1d]	3289	1			T3	1		T6	16		T7	8
valid_sources[0x1e]	3391	1			T3	9		T6	3		T7	2
valid_sources[0x1f]	5587	1			T3	2		T6	3		T15	11
valid_sources[0x20]	7682	1			T6	3		T7	9		T8	5
valid_sources[0x21]	4246	1			T3	1		T6	19		T7	4
valid_sources[0x22]	4221	1			T3	3		T6	3		T12	1
valid_sources[0x23]	3426	1			T3	1		T6	1		T7	1
valid_sources[0x24]	3355	1			T3	4		T7	7		T15	22
valid_sources[0x25]	3872	1			T6	5		T7	3		T15	9
valid_sources[0x26]	4503	1			T3	3		T6	1		T8	7
valid_sources[0x27]	3565	1			T6	1		T7	8		T8	1
valid_sources[0x28]	4819	1			T3	1		T6	2		T8	4
valid_sources[0x29]	5276	1			T6	5		T7	18		T15	5
valid_sources[0x2a]	3451	1			T3	4		T6	1		T7	2
valid_sources[0x2b]	6258	1			T3	7		T7	10		T8	4
valid_sources[0x2c]	3984	1			T3	3		T8	3		T15	12
valid_sources[0x2d]	8106	1			T6	1		T7	3		T8	4
valid_sources[0x2e]	3286	1			T3	3		T6	1		T7	14
valid_sources[0x2f]	4551	1			T3	3		T6	6		T7	4
valid_sources[0x30]	3722	1			T3	6		T6	5		T7	1
valid_sources[0x31]	3696	1			T3	1		T8	1		T15	4
valid_sources[0x32]	3330	1			T2	1		T3	1		T6	4
valid_sources[0x33]	3041	1			T7	4		T8	6		T15	23
valid_sources[0x34]	4128	1			T3	3		T6	10		T8	3
valid_sources[0x35]	4178	1			T3	1		T6	5		T7	12
valid_sources[0x36]	5099	1			T3	4		T6	15		T7	3
valid_sources[0x37]	3297	1			T3	5		T6	7		T8	7
valid_sources[0x38]	3841	1			T3	2		T6	3		T7	2
valid_sources[0x39]	3613	1			T3	3		T6	3		T8	3
valid_sources[0x3a]	3404	1			T6	4		T7	3		T8	2
valid_sources[0x3b]	3261	1			T3	1		T6	4		T7	2
valid_sources[0x3c]	3349	1			T3	2		T6	4		T7	20
valid_sources[0x3d]	3742	1			T3	3		T6	3		T7	2
valid_sources[0x3e]	3805	1			T3	3		T6	2		T7	2
valid_sources[0x3f]	3851	1			T3	3		T6	9		T7	5
valid_sources[0x40]	3900	1			T3	2		T6	4		T7	5
valid_sources[0x41]	4353	1			T3	4		T6	2		T7	2
valid_sources[0x42]	5052	1			T2	1		T3	5		T7	1
valid_sources[0x43]	3777	1			T3	3		T6	14		T7	2
valid_sources[0x44]	3407	1			T6	6		T7	6		T8	1
valid_sources[0x45]	3487	1			T3	1		T6	2		T7	5
valid_sources[0x46]	4426	1			T3	2		T6	6		T8	6
valid_sources[0x47]	3143	1			T3	8		T6	1		T8	6
valid_sources[0x48]	3334	1			T6	3		T7	2		T8	2
valid_sources[0x49]	3373	1			T3	2		T6	4		T7	7
valid_sources[0x4a]	3914	1			T3	6		T7	14		T8	2
valid_sources[0x4b]	5303	1			T3	2		T6	4		T7	1
valid_sources[0x4c]	4708	1			T3	1		T6	6		T7	7
valid_sources[0x4d]	4939	1			T3	11		T8	4		T15	13
valid_sources[0x4e]	3622	1			T3	1		T6	3		T15	7
valid_sources[0x4f]	3224	1			T3	2		T6	3		T7	4
valid_sources[0x50]	4949	1			T3	4		T6	3		T7	1
valid_sources[0x51]	3074	1			T3	2		T6	2		T8	3
valid_sources[0x52]	4295	1			T3	5		T6	8		T7	5
valid_sources[0x53]	3707	1			T3	1		T6	13		T8	4
valid_sources[0x54]	3861	1			T3	4		T6	8		T7	1
valid_sources[0x55]	3443	1			T2	1		T6	5		T8	5
valid_sources[0x56]	3899	1			T3	4		T6	5		T7	2
valid_sources[0x57]	3967	1			T3	5		T6	2		T8	10
valid_sources[0x58]	3967	1			T3	3		T6	5		T7	1
valid_sources[0x59]	3933	1			T3	4		T7	4		T8	5
valid_sources[0x5a]	3920	1			T2	1		T3	2		T6	5
valid_sources[0x5b]	3286	1			T2	3		T3	2		T7	2
valid_sources[0x5c]	3816	1			T3	1		T6	3		T15	7
valid_sources[0x5d]	5117	1			T6	1		T8	5		T15	16
valid_sources[0x5e]	4758	1			T6	3		T7	1		T10	212
valid_sources[0x5f]	4120	1			T3	1		T6	4		T8	15
valid_sources[0x60]	3601	1			T3	5		T6	3		T7	2
valid_sources[0x61]	4699	1			T2	1		T3	2		T6	5
valid_sources[0x62]	3307	1			T3	4		T6	3		T15	21
valid_sources[0x63]	4132	1			T3	5		T6	4		T8	3
valid_sources[0x64]	7092	1			T3	2		T6	2		T7	3
valid_sources[0x65]	4649	1			T3	6		T6	1		T7	1
valid_sources[0x66]	3196	1			T8	1		T16	8		T17	2
valid_sources[0x67]	3491	1			T3	8		T6	3		T7	4
valid_sources[0x68]	3323	1			T3	1		T6	10		T15	5
valid_sources[0x69]	3851	1			T3	2		T6	5		T7	2
valid_sources[0x6a]	4132	1			T3	4		T6	8		T7	7
valid_sources[0x6b]	3537	1			T3	1		T6	3		T7	3
valid_sources[0x6c]	3410	1			T3	2		T6	11		T7	10
valid_sources[0x6d]	3376	1			T3	11		T6	1		T7	2
valid_sources[0x6e]	6743	1			T3	2		T6	5		T8	5
valid_sources[0x6f]	3846	1			T3	10		T6	9		T8	6
valid_sources[0x70]	3180	1			T3	4		T6	4		T8	2
valid_sources[0x71]	3503	1			T3	3		T6	5		T7	3
valid_sources[0x72]	6770	1			T3	1		T6	2		T7	1
valid_sources[0x73]	3547	1			T8	5		T15	6		T16	32
valid_sources[0x74]	3953	1			T6	4		T7	4		T8	1
valid_sources[0x75]	3648	1			T3	4		T6	4		T7	8
valid_sources[0x76]	4081	1			T3	5		T6	3		T7	11
valid_sources[0x77]	3375	1			T3	2		T6	6		T7	13
valid_sources[0x78]	4430	1			T3	2		T6	12		T7	2
valid_sources[0x79]	3418	1			T3	3		T6	8		T7	7
valid_sources[0x7a]	4427	1			T3	4		T6	8		T7	2
valid_sources[0x7b]	3439	1			T3	3		T6	5		T7	5
valid_sources[0x7c]	4740	1			T3	2		T6	8		T8	4
valid_sources[0x7d]	3427	1			T3	1		T6	4		T8	4
valid_sources[0x7e]	4262	1			T2	1		T6	4		T8	1
valid_sources[0x7f]	4580	1			T2	1		T6	8		T7	3
valid_sources[0x80]	4390	1			T3	5		T6	3		T15	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

257360

1

T3

192

T6

284

T7

213

values[0x0]

all_enables

biggest_size

83238

1

T2

7

T3

69

T6

78

values[0x1]

all_enables

biggest_size

44654

1

T2

3

T3

38

T4

1