Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T5,T10

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T5,T10

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T5,T10

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T5,T10

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T5,T10

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T5,T10

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T5,T10

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T5,T10

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13426666	14498	0	0
gen_assertions[0].RstEnOn_A	13426666	1022	0	0
gen_assertions[0].RstNOff_A	13426666	14498	0	0
gen_assertions[0].RstNOn_A	13426666	1022	0	0
gen_assertions[1].RstEnOff_A	53706220	13192	0	0
gen_assertions[1].RstEnOn_A	53706220	999	0	0
gen_assertions[1].RstNOff_A	53706220	13192	0	0
gen_assertions[1].RstNOn_A	53706220	999	0	0
gen_assertions[2].RstEnOff_A	26854187	13286	0	0
gen_assertions[2].RstEnOn_A	26854187	1054	0	0
gen_assertions[2].RstNOff_A	26854187	13286	0	0
gen_assertions[2].RstNOn_A	26854187	1054	0	0
gen_assertions[3].RstEnOff_A	26854130	13319	0	0
gen_assertions[3].RstEnOn_A	26854130	1077	0	0
gen_assertions[3].RstNOff_A	26854130	13319	0	0
gen_assertions[3].RstNOn_A	26854130	1077	0	0
gen_assertions[4].RstEnOff_A	1696262	22430	0	0
gen_assertions[4].RstEnOn_A	1696262	1108	0	0
gen_assertions[4].RstNOff_A	1696262	22430	0	0
gen_assertions[4].RstNOn_A	1696262	1108	0	0
gen_assertions[5].RstEnOff_A	13426666	14731	0	0
gen_assertions[5].RstEnOn_A	13426666	1152	0	0
gen_assertions[5].RstNOff_A	13426666	14731	0	0
gen_assertions[5].RstNOn_A	13426666	1152	0	0
gen_assertions[6].RstEnOff_A	13426666	14820	0	0
gen_assertions[6].RstEnOn_A	13426666	1245	0	0
gen_assertions[6].RstNOff_A	13426666	14820	0	0
gen_assertions[6].RstNOn_A	13426666	1245	0	0
gen_assertions[7].RstEnOff_A	13426666	14845	0	0
gen_assertions[7].RstEnOn_A	13426666	1266	0	0
gen_assertions[7].RstNOff_A	13426666	14845	0	0
gen_assertions[7].RstNOn_A	13426666	1266	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	14498	0	0
T3	7199	3	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	5	0	0
T7	3066	2	0	0
T8	3144	2	0	0
T9	2142	0	0	0
T10	2552	4	0	0
T11	4416	4	0	0
T12	5236	0	0	0
T14	0	3	0	0
T15	0	34	0	0
T16	0	75	0	0
T21	0	1	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	1022	0	0
T3	7199	3	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	5	0	0
T7	3066	2	0	0
T8	3144	2	0	0
T9	2142	0	0	0
T10	2552	0	0	0
T11	4416	0	0	0
T12	5236	0	0	0
T14	0	3	0	0
T21	0	1	0	0
T43	0	7	0	0
T51	0	11	0	0
T89	0	2	0	0
T90	0	8	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	14498	0	0
T3	7199	3	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	5	0	0
T7	3066	2	0	0
T8	3144	2	0	0
T9	2142	0	0	0
T10	2552	4	0	0
T11	4416	4	0	0
T12	5236	0	0	0
T14	0	3	0	0
T15	0	34	0	0
T16	0	75	0	0
T21	0	1	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	1022	0	0
T3	7199	3	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	5	0	0
T7	3066	2	0	0
T8	3144	2	0	0
T9	2142	0	0	0
T10	2552	0	0	0
T11	4416	0	0	0
T12	5236	0	0	0
T14	0	3	0	0
T21	0	1	0	0
T43	0	7	0	0
T51	0	11	0	0
T89	0	2	0	0
T90	0	8	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53706220	13192	0	0
T3	28796	3	0	0
T4	7063	0	0	0
T5	23367	0	0	0
T6	14565	7	0	0
T7	12270	3	0	0
T8	12583	5	0	0
T9	8571	0	0	0
T10	10219	4	0	0
T11	17664	4	0	0
T12	20948	0	0	0
T14	0	6	0	0
T15	0	30	0	0
T16	0	61	0	0
T21	0	2	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53706220	999	0	0
T3	28796	3	0	0
T4	7063	0	0	0
T5	23367	0	0	0
T6	14565	7	0	0
T7	12270	3	0	0
T8	12583	5	0	0
T9	8571	0	0	0
T10	10219	0	0	0
T11	17664	0	0	0
T12	20948	0	0	0
T14	0	6	0	0
T21	0	2	0	0
T43	0	8	0	0
T51	0	9	0	0
T90	0	6	0	0
T91	0	7	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53706220	13192	0	0
T3	28796	3	0	0
T4	7063	0	0	0
T5	23367	0	0	0
T6	14565	7	0	0
T7	12270	3	0	0
T8	12583	5	0	0
T9	8571	0	0	0
T10	10219	4	0	0
T11	17664	4	0	0
T12	20948	0	0	0
T14	0	6	0	0
T15	0	30	0	0
T16	0	61	0	0
T21	0	2	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53706220	999	0	0
T3	28796	3	0	0
T4	7063	0	0	0
T5	23367	0	0	0
T6	14565	7	0	0
T7	12270	3	0	0
T8	12583	5	0	0
T9	8571	0	0	0
T10	10219	0	0	0
T11	17664	0	0	0
T12	20948	0	0	0
T14	0	6	0	0
T21	0	2	0	0
T43	0	8	0	0
T51	0	9	0	0
T90	0	6	0	0
T91	0	7	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854187	13286	0	0
T3	14398	5	0	0
T4	3531	0	0	0
T5	11677	0	0	0
T6	7282	9	0	0
T7	6135	4	0	0
T8	6291	5	0	0
T9	4286	0	0	0
T10	5110	4	0	0
T11	8831	4	0	0
T12	10473	0	0	0
T14	0	9	0	0
T15	0	30	0	0
T16	0	61	0	0
T21	0	3	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854187	1054	0	0
T3	14398	5	0	0
T4	3531	0	0	0
T5	11677	0	0	0
T6	7282	9	0	0
T7	6135	4	0	0
T8	6291	5	0	0
T9	4286	0	0	0
T10	5110	0	0	0
T11	8831	0	0	0
T12	10473	0	0	0
T14	0	9	0	0
T21	0	3	0	0
T43	0	9	0	0
T51	0	10	0	0
T90	0	1	0	0
T91	0	10	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854187	13286	0	0
T3	14398	5	0	0
T4	3531	0	0	0
T5	11677	0	0	0
T6	7282	9	0	0
T7	6135	4	0	0
T8	6291	5	0	0
T9	4286	0	0	0
T10	5110	4	0	0
T11	8831	4	0	0
T12	10473	0	0	0
T14	0	9	0	0
T15	0	30	0	0
T16	0	61	0	0
T21	0	3	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854187	1054	0	0
T3	14398	5	0	0
T4	3531	0	0	0
T5	11677	0	0	0
T6	7282	9	0	0
T7	6135	4	0	0
T8	6291	5	0	0
T9	4286	0	0	0
T10	5110	0	0	0
T11	8831	0	0	0
T12	10473	0	0	0
T14	0	9	0	0
T21	0	3	0	0
T43	0	9	0	0
T51	0	10	0	0
T90	0	1	0	0
T91	0	10	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854130	13319	0	0
T3	14398	6	0	0
T4	3531	0	0	0
T5	11675	0	0	0
T6	7282	8	0	0
T7	6136	5	0	0
T8	6291	7	0	0
T9	4285	0	0	0
T10	5109	4	0	0
T11	8832	4	0	0
T12	10473	0	0	0
T14	0	8	0	0
T15	0	30	0	0
T16	0	61	0	0
T21	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854130	1077	0	0
T3	14398	6	0	0
T4	3531	0	0	0
T5	11675	0	0	0
T6	7282	8	0	0
T7	6136	5	0	0
T8	6291	7	0	0
T9	4285	0	0	0
T10	5109	0	0	0
T11	8832	0	0	0
T12	10473	0	0	0
T14	0	8	0	0
T21	0	4	0	0
T43	0	10	0	0
T51	0	11	0	0
T58	0	20	0	0
T91	0	11	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854130	13319	0	0
T3	14398	6	0	0
T4	3531	0	0	0
T5	11675	0	0	0
T6	7282	8	0	0
T7	6136	5	0	0
T8	6291	7	0	0
T9	4285	0	0	0
T10	5109	4	0	0
T11	8832	4	0	0
T12	10473	0	0	0
T14	0	8	0	0
T15	0	30	0	0
T16	0	61	0	0
T21	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854130	1077	0	0
T3	14398	6	0	0
T4	3531	0	0	0
T5	11675	0	0	0
T6	7282	8	0	0
T7	6136	5	0	0
T8	6291	7	0	0
T9	4285	0	0	0
T10	5109	0	0	0
T11	8832	0	0	0
T12	10473	0	0	0
T14	0	8	0	0
T21	0	4	0	0
T43	0	10	0	0
T51	0	11	0	0
T58	0	20	0	0
T91	0	11	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696262	22430	0	0
T1	730	2	0	0
T2	211	1	0	0
T3	898	6	0	0
T4	219	1	0	0
T5	732	3	0	0
T6	453	13	0	0
T7	383	7	0	0
T8	392	9	0	0
T9	266	1	0	0
T10	318	5	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696262	1108	0	0
T3	898	5	0	0
T4	219	0	0	0
T5	732	0	0	0
T6	453	12	0	0
T7	383	6	0	0
T8	392	8	0	0
T9	266	0	0	0
T10	318	0	0	0
T11	550	0	0	0
T12	654	0	0	0
T14	0	11	0	0
T21	0	5	0	0
T43	0	11	0	0
T51	0	10	0	0
T58	0	20	0	0
T91	0	11	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696262	22430	0	0
T1	730	2	0	0
T2	211	1	0	0
T3	898	6	0	0
T4	219	1	0	0
T5	732	3	0	0
T6	453	13	0	0
T7	383	7	0	0
T8	392	9	0	0
T9	266	1	0	0
T10	318	5	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696262	1108	0	0
T3	898	5	0	0
T4	219	0	0	0
T5	732	0	0	0
T6	453	12	0	0
T7	383	6	0	0
T8	392	8	0	0
T9	266	0	0	0
T10	318	0	0	0
T11	550	0	0	0
T12	654	0	0	0
T14	0	11	0	0
T21	0	5	0	0
T43	0	11	0	0
T51	0	10	0	0
T58	0	20	0	0
T91	0	11	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	14731	0	0
T3	7199	7	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	12	0	0
T7	3066	7	0	0
T8	3144	8	0	0
T9	2142	0	0	0
T10	2552	4	0	0
T11	4416	4	0	0
T12	5236	0	0	0
T14	0	11	0	0
T15	0	34	0	0
T16	0	75	0	0
T21	0	6	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	1152	0	0
T3	7199	7	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	12	0	0
T7	3066	7	0	0
T8	3144	8	0	0
T9	2142	0	0	0
T10	2552	0	0	0
T11	4416	0	0	0
T12	5236	0	0	0
T14	0	11	0	0
T21	0	6	0	0
T43	0	10	0	0
T51	0	7	0	0
T58	0	20	0	0
T91	0	9	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	14731	0	0
T3	7199	7	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	12	0	0
T7	3066	7	0	0
T8	3144	8	0	0
T9	2142	0	0	0
T10	2552	4	0	0
T11	4416	4	0	0
T12	5236	0	0	0
T14	0	11	0	0
T15	0	34	0	0
T16	0	75	0	0
T21	0	6	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	1152	0	0
T3	7199	7	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	12	0	0
T7	3066	7	0	0
T8	3144	8	0	0
T9	2142	0	0	0
T10	2552	0	0	0
T11	4416	0	0	0
T12	5236	0	0	0
T14	0	11	0	0
T21	0	6	0	0
T43	0	10	0	0
T51	0	7	0	0
T58	0	20	0	0
T91	0	9	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	14820	0	0
T3	7199	8	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	13	0	0
T7	3066	9	0	0
T8	3144	9	0	0
T9	2142	0	0	0
T10	2552	4	0	0
T11	4416	4	0	0
T12	5236	0	0	0
T14	0	13	0	0
T15	0	34	0	0
T16	0	75	0	0
T21	0	7	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	1245	0	0
T3	7199	8	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	13	0	0
T7	3066	9	0	0
T8	3144	9	0	0
T9	2142	0	0	0
T10	2552	0	0	0
T11	4416	0	0	0
T12	5236	0	0	0
T14	0	13	0	0
T21	0	7	0	0
T43	0	13	0	0
T51	0	13	0	0
T58	0	19	0	0
T91	0	15	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	14820	0	0
T3	7199	8	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	13	0	0
T7	3066	9	0	0
T8	3144	9	0	0
T9	2142	0	0	0
T10	2552	4	0	0
T11	4416	4	0	0
T12	5236	0	0	0
T14	0	13	0	0
T15	0	34	0	0
T16	0	75	0	0
T21	0	7	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	1245	0	0
T3	7199	8	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	13	0	0
T7	3066	9	0	0
T8	3144	9	0	0
T9	2142	0	0	0
T10	2552	0	0	0
T11	4416	0	0	0
T12	5236	0	0	0
T14	0	13	0	0
T21	0	7	0	0
T43	0	13	0	0
T51	0	13	0	0
T58	0	19	0	0
T91	0	15	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	14845	0	0
T3	7199	9	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	15	0	0
T7	3066	8	0	0
T8	3144	12	0	0
T9	2142	0	0	0
T10	2552	4	0	0
T11	4416	4	0	0
T12	5236	0	0	0
T14	0	15	0	0
T15	0	34	0	0
T16	0	75	0	0
T21	0	7	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	1266	0	0
T3	7199	9	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	15	0	0
T7	3066	8	0	0
T8	3144	12	0	0
T9	2142	0	0	0
T10	2552	0	0	0
T11	4416	0	0	0
T12	5236	0	0	0
T14	0	15	0	0
T21	0	7	0	0
T43	0	14	0	0
T51	0	13	0	0
T58	0	18	0	0
T91	0	17	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	14845	0	0
T3	7199	9	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	15	0	0
T7	3066	8	0	0
T8	3144	12	0	0
T9	2142	0	0	0
T10	2552	4	0	0
T11	4416	4	0	0
T12	5236	0	0	0
T14	0	15	0	0
T15	0	34	0	0
T16	0	75	0	0
T21	0	7	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	1266	0	0
T3	7199	9	0	0
T4	1765	0	0	0
T5	5837	0	0	0
T6	3640	15	0	0
T7	3066	8	0	0
T8	3144	12	0	0
T9	2142	0	0	0
T10	2552	0	0	0
T11	4416	0	0	0
T12	5236	0	0	0
T14	0	15	0	0
T21	0	7	0	0
T43	0	14	0	0
T51	0	13	0	0
T58	0	18	0	0
T91	0	17	0	0