Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12689444	7382	0	0
alert_regwen_rd_A	12689444	4874	0	0
cpu_regwen_rd_A	12689444	4871	0	0
sw_rst_ctrl_n_0_rd_A	12689444	9852	0	0
sw_rst_ctrl_n_1_rd_A	12689444	9921	0	0
sw_rst_ctrl_n_2_rd_A	12689444	10010	0	0
sw_rst_ctrl_n_3_rd_A	12689444	9825	0	0
sw_rst_ctrl_n_4_rd_A	12689444	9519	0	0
sw_rst_ctrl_n_5_rd_A	12689444	9610	0	0
sw_rst_ctrl_n_6_rd_A	12689444	9622	0	0
sw_rst_ctrl_n_7_rd_A	12689444	9595	0	0
sw_rst_regwen_0_rd_A	12689444	5243	0	0
sw_rst_regwen_1_rd_A	12689444	5407	0	0
sw_rst_regwen_2_rd_A	12689444	5365	0	0
sw_rst_regwen_3_rd_A	12689444	5441	0	0
sw_rst_regwen_4_rd_A	12689444	5598	0	0
sw_rst_regwen_5_rd_A	12689444	5399	0	0
sw_rst_regwen_6_rd_A	12689444	5293	0	0
sw_rst_regwen_7_rd_A	12689444	4953	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	7382	0	0
T66	4814	19	0	0
T67	10216	347	0	0
T68	4803	149	0	0
T69	4342	93	0	0
T70	5507	284	0	0
T71	12508	532	0	0
T75	4367	80	0	0
T76	2472	6	0	0
T92	3769	132	0	0
T93	10856	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	4874	0	0
T19	37683	70	0	0
T20	32025	43	0	0
T22	4548	0	0	0
T23	3055	0	0	0
T32	4560	0	0	0
T33	124324	0	0	0
T43	8678	0	0	0
T51	130280	0	0	0
T58	0	343	0	0
T89	1657	0	0	0
T96	0	44	0	0
T99	0	60	0	0
T102	0	82	0	0
T103	0	48	0	0
T104	0	143	0	0
T107	0	26	0	0
T130	0	40	0	0
T131	1568	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	4871	0	0
T19	37683	65	0	0
T20	32025	42	0	0
T22	4548	0	0	0
T23	3055	0	0	0
T32	4560	0	0	0
T33	124324	0	0	0
T43	8678	0	0	0
T51	130280	0	0	0
T58	0	324	0	0
T89	1657	0	0	0
T96	0	59	0	0
T99	0	90	0	0
T102	0	59	0	0
T103	0	25	0	0
T104	0	160	0	0
T107	0	36	0	0
T130	0	34	0	0
T131	1568	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	9852	0	0
T14	10690	124	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	57	0	0
T20	32025	47	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T32	0	59	0	0
T58	0	657	0	0
T96	0	69	0	0
T99	0	88	0	0
T102	0	98	0	0
T107	0	41	0	0
T132	0	88	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	9921	0	0
T14	10690	115	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	41	0	0
T20	32025	54	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T32	0	47	0	0
T58	0	590	0	0
T96	0	64	0	0
T99	0	56	0	0
T102	0	95	0	0
T107	0	36	0	0
T132	0	41	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	10010	0	0
T14	10690	125	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	58	0	0
T20	32025	49	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T32	0	53	0	0
T58	0	639	0	0
T96	0	62	0	0
T99	0	62	0	0
T102	0	66	0	0
T107	0	44	0	0
T132	0	47	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	9825	0	0
T14	10690	136	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	55	0	0
T20	32025	14	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T32	0	47	0	0
T58	0	552	0	0
T96	0	59	0	0
T99	0	75	0	0
T102	0	91	0	0
T107	0	37	0	0
T132	0	76	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	9519	0	0
T14	10690	53	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	59	0	0
T20	32025	28	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T32	0	37	0	0
T58	0	608	0	0
T96	0	51	0	0
T99	0	72	0	0
T102	0	60	0	0
T107	0	29	0	0
T132	0	74	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	9610	0	0
T14	10690	125	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	50	0	0
T20	32025	58	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T32	0	34	0	0
T58	0	619	0	0
T96	0	47	0	0
T99	0	71	0	0
T102	0	82	0	0
T107	0	34	0	0
T132	0	62	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	9622	0	0
T14	10690	132	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	49	0	0
T20	32025	54	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T32	0	59	0	0
T58	0	542	0	0
T96	0	68	0	0
T99	0	68	0	0
T102	0	89	0	0
T107	0	36	0	0
T132	0	62	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	9595	0	0
T14	10690	104	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	52	0	0
T20	32025	36	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T32	0	39	0	0
T58	0	608	0	0
T96	0	68	0	0
T99	0	77	0	0
T102	0	85	0	0
T107	0	31	0	0
T132	0	61	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	5243	0	0
T14	10690	16	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	52	0	0
T20	32025	47	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T58	0	384	0	0
T96	0	44	0	0
T99	0	75	0	0
T102	0	96	0	0
T107	0	26	0	0
T130	0	21	0	0
T133	0	24	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	5407	0	0
T14	10690	16	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	53	0	0
T20	32025	39	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T58	0	355	0	0
T96	0	52	0	0
T99	0	92	0	0
T102	0	113	0	0
T107	0	35	0	0
T130	0	27	0	0
T133	0	19	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	5365	0	0
T14	10690	26	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	68	0	0
T20	32025	51	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T58	0	374	0	0
T96	0	65	0	0
T99	0	64	0	0
T102	0	79	0	0
T107	0	25	0	0
T130	0	32	0	0
T133	0	12	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	5441	0	0
T14	10690	24	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	53	0	0
T20	32025	39	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T58	0	322	0	0
T96	0	50	0	0
T99	0	76	0	0
T102	0	84	0	0
T107	0	38	0	0
T130	0	46	0	0
T133	0	23	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	5598	0	0
T14	10690	40	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	57	0	0
T20	32025	27	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T58	0	402	0	0
T96	0	84	0	0
T99	0	88	0	0
T102	0	79	0	0
T107	0	33	0	0
T130	0	37	0	0
T133	0	7	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	5399	0	0
T14	10690	28	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	42	0	0
T20	32025	67	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T58	0	365	0	0
T96	0	62	0	0
T99	0	65	0	0
T102	0	119	0	0
T107	0	37	0	0
T130	0	42	0	0
T133	0	23	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	5293	0	0
T14	10690	14	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	42	0	0
T20	32025	60	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T58	0	382	0	0
T96	0	65	0	0
T99	0	83	0	0
T102	0	71	0	0
T107	0	29	0	0
T130	0	37	0	0
T133	0	23	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12689444	4953	0	0
T14	10690	26	0	0
T15	14569	0	0	0
T16	26250	0	0	0
T17	3916	0	0	0
T18	30666	0	0	0
T19	37683	57	0	0
T20	32025	50	0	0
T21	6056	0	0	0
T30	1511	0	0	0
T31	1739	0	0	0
T58	0	296	0	0
T96	0	53	0	0
T99	0	52	0	0
T102	0	89	0	0
T107	0	43	0	0
T130	0	34	0	0
T133	0	13	0	0