Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T5,T10

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11921101	13613	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11921101	125513	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11921101	7068072	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11921101	199918	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11921101	13613	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11921101	125513	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11921101	7068072	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11921101	199918	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	13613	0	0
T10	2360	4	0	0
T11	4173	4	0	0
T12	5073	0	0	0
T13	2816	0	0	0
T14	10690	0	0	0
T15	14569	34	0	0
T16	26250	75	0	0
T17	3916	4	0	0
T18	30666	41	0	0
T19	0	39	0	0
T20	0	33	0	0
T21	6056	0	0	0
T32	0	14	0	0
T33	0	160	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	125513	0	0
T10	2360	38	0	0
T11	4173	38	0	0
T12	5073	0	0	0
T13	2816	0	0	0
T14	10690	0	0	0
T15	14569	307	0	0
T16	26250	701	0	0
T17	3916	38	0	0
T18	30666	383	0	0
T19	0	356	0	0
T20	0	303	0	0
T21	6056	0	0	0
T32	0	126	0	0
T33	0	1461	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	7068072	0	0
T1	5478	562	0	0
T2	1625	1032	0	0
T3	7108	6532	0	0
T4	1698	1098	0	0
T5	5294	572	0	0
T6	3622	2974	0	0
T7	3001	2411	0	0
T8	3078	2487	0	0
T9	2123	1476	0	0
T10	2360	1367	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	199918	0	0
T10	2360	70	0	0
T11	4173	55	0	0
T12	5073	0	0	0
T13	2816	0	0	0
T14	10690	0	0	0
T15	14569	469	0	0
T16	26250	1119	0	0
T17	3916	62	0	0
T18	30666	620	0	0
T19	0	579	0	0
T20	0	480	0	0
T21	6056	0	0	0
T32	0	203	0	0
T33	0	2295	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	13613	0	0
T10	2360	4	0	0
T11	4173	4	0	0
T12	5073	0	0	0
T13	2816	0	0	0
T14	10690	0	0	0
T15	14569	34	0	0
T16	26250	75	0	0
T17	3916	4	0	0
T18	30666	41	0	0
T19	0	39	0	0
T20	0	33	0	0
T21	6056	0	0	0
T32	0	14	0	0
T33	0	160	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	125513	0	0
T10	2360	38	0	0
T11	4173	38	0	0
T12	5073	0	0	0
T13	2816	0	0	0
T14	10690	0	0	0
T15	14569	307	0	0
T16	26250	701	0	0
T17	3916	38	0	0
T18	30666	383	0	0
T19	0	356	0	0
T20	0	303	0	0
T21	6056	0	0	0
T32	0	126	0	0
T33	0	1461	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	7068072	0	0
T1	5478	562	0	0
T2	1625	1032	0	0
T3	7108	6532	0	0
T4	1698	1098	0	0
T5	5294	572	0	0
T6	3622	2974	0	0
T7	3001	2411	0	0
T8	3078	2487	0	0
T9	2123	1476	0	0
T10	2360	1367	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	199918	0	0
T10	2360	70	0	0
T11	4173	55	0	0
T12	5073	0	0	0
T13	2816	0	0	0
T14	10690	0	0	0
T15	14569	469	0	0
T16	26250	1119	0	0
T17	3916	62	0	0
T18	30666	620	0	0
T19	0	579	0	0
T20	0	480	0	0
T21	6056	0	0	0
T32	0	203	0	0
T33	0	2295	0	0