Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T15
0	1	Covered	T10,T15,T17
1	0	Covered	T15,T18,T19

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T12
1	0	Covered	T10,T11,T15
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55946483	8938	0	0
CascadeEffAonToRstPorAboveRise_A	55946483	8938	0	0
CascadeEffAonToRstPorIoAboveFall_A	53706220	8938	0	0
CascadeEffAonToRstPorIoAboveRise_A	53706220	8938	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26854187	8938	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26854187	8938	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13426666	8938	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13426666	8938	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26854130	8938	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26854130	8938	0	0
CascadeLcToLcAboveFall_A	55946483	22551	0	0
CascadeLcToLcAboveRise_A	55946483	22551	0	0
CascadeLcToLcAonAboveFall_A	1696262	22551	0	0
CascadeLcToLcAonAboveRise_A	1696262	22551	0	0
CascadeLcToLcShadowedAboveFall_A	55946483	22551	0	0
CascadeLcToLcShadowedAboveRise_A	55946483	22551	0	0
CascadePorToAonAboveFall_A	1696262	7043	0	0
CascadeSysToSysAboveFall_A	55946483	22551	0	0
CascadeSysToSysAboveRise_A	55946483	22551	0	0
ScanRstToAonRise_A	1696262	259	0	0
StablePorToAonRise_A	1696262	8938	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11921101	22551	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11921101	22551	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11921101	22551	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11921101	22551	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13426666	22551	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13426666	22551	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11921101	22551	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11921101	22551	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11921101	22551	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11921101	22551	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55946483	8938	0	0
T1	24291	8	0	0
T2	7054	1	0	0
T3	29998	1	0	0
T4	7359	1	0	0
T5	24330	8	0	0
T6	15173	1	0	0
T7	12783	1	0	0
T8	13107	1	0	0
T9	8929	1	0	0
T10	10642	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55946483	8938	0	0
T1	24291	8	0	0
T2	7054	1	0	0
T3	29998	1	0	0
T4	7359	1	0	0
T5	24330	8	0	0
T6	15173	1	0	0
T7	12783	1	0	0
T8	13107	1	0	0
T9	8929	1	0	0
T10	10642	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53706220	8938	0	0
T1	23336	8	0	0
T2	6771	1	0	0
T3	28796	1	0	0
T4	7063	1	0	0
T5	23367	8	0	0
T6	14565	1	0	0
T7	12270	1	0	0
T8	12583	1	0	0
T9	8571	1	0	0
T10	10219	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53706220	8938	0	0
T1	23336	8	0	0
T2	6771	1	0	0
T3	28796	1	0	0
T4	7063	1	0	0
T5	23367	8	0	0
T6	14565	1	0	0
T7	12270	1	0	0
T8	12583	1	0	0
T9	8571	1	0	0
T10	10219	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854187	8938	0	0
T1	11663	8	0	0
T2	3385	1	0	0
T3	14398	1	0	0
T4	3531	1	0	0
T5	11677	8	0	0
T6	7282	1	0	0
T7	6135	1	0	0
T8	6291	1	0	0
T9	4286	1	0	0
T10	5110	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854187	8938	0	0
T1	11663	8	0	0
T2	3385	1	0	0
T3	14398	1	0	0
T4	3531	1	0	0
T5	11677	8	0	0
T6	7282	1	0	0
T7	6135	1	0	0
T8	6291	1	0	0
T9	4286	1	0	0
T10	5110	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	8938	0	0
T1	5831	8	0	0
T2	1691	1	0	0
T3	7199	1	0	0
T4	1765	1	0	0
T5	5837	8	0	0
T6	3640	1	0	0
T7	3066	1	0	0
T8	3144	1	0	0
T9	2142	1	0	0
T10	2552	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	8938	0	0
T1	5831	8	0	0
T2	1691	1	0	0
T3	7199	1	0	0
T4	1765	1	0	0
T5	5837	8	0	0
T6	3640	1	0	0
T7	3066	1	0	0
T8	3144	1	0	0
T9	2142	1	0	0
T10	2552	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854130	8938	0	0
T1	11656	8	0	0
T2	3384	1	0	0
T3	14398	1	0	0
T4	3531	1	0	0
T5	11675	8	0	0
T6	7282	1	0	0
T7	6136	1	0	0
T8	6291	1	0	0
T9	4285	1	0	0
T10	5109	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26854130	8938	0	0
T1	11656	8	0	0
T2	3384	1	0	0
T3	14398	1	0	0
T4	3531	1	0	0
T5	11675	8	0	0
T6	7282	1	0	0
T7	6136	1	0	0
T8	6291	1	0	0
T9	4285	1	0	0
T10	5109	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55946483	22551	0	0
T1	24291	8	0	0
T2	7054	1	0	0
T3	29998	1	0	0
T4	7359	1	0	0
T5	24330	8	0	0
T6	15173	1	0	0
T7	12783	1	0	0
T8	13107	1	0	0
T9	8929	1	0	0
T10	10642	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55946483	22551	0	0
T1	24291	8	0	0
T2	7054	1	0	0
T3	29998	1	0	0
T4	7359	1	0	0
T5	24330	8	0	0
T6	15173	1	0	0
T7	12783	1	0	0
T8	13107	1	0	0
T9	8929	1	0	0
T10	10642	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696262	22551	0	0
T1	730	8	0	0
T2	211	1	0	0
T3	898	1	0	0
T4	219	1	0	0
T5	732	8	0	0
T6	453	1	0	0
T7	383	1	0	0
T8	392	1	0	0
T9	266	1	0	0
T10	318	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696262	22551	0	0
T1	730	8	0	0
T2	211	1	0	0
T3	898	1	0	0
T4	219	1	0	0
T5	732	8	0	0
T6	453	1	0	0
T7	383	1	0	0
T8	392	1	0	0
T9	266	1	0	0
T10	318	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55946483	22551	0	0
T1	24291	8	0	0
T2	7054	1	0	0
T3	29998	1	0	0
T4	7359	1	0	0
T5	24330	8	0	0
T6	15173	1	0	0
T7	12783	1	0	0
T8	13107	1	0	0
T9	8929	1	0	0
T10	10642	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55946483	22551	0	0
T1	24291	8	0	0
T2	7054	1	0	0
T3	29998	1	0	0
T4	7359	1	0	0
T5	24330	8	0	0
T6	15173	1	0	0
T7	12783	1	0	0
T8	13107	1	0	0
T9	8929	1	0	0
T10	10642	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696262	7043	0	0
T1	730	8	0	0
T2	211	1	0	0
T3	898	1	0	0
T4	219	1	0	0
T5	732	8	0	0
T6	453	1	0	0
T7	383	1	0	0
T8	392	1	0	0
T9	266	1	0	0
T10	318	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55946483	22551	0	0
T1	24291	8	0	0
T2	7054	1	0	0
T3	29998	1	0	0
T4	7359	1	0	0
T5	24330	8	0	0
T6	15173	1	0	0
T7	12783	1	0	0
T8	13107	1	0	0
T9	8929	1	0	0
T10	10642	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55946483	22551	0	0
T1	24291	8	0	0
T2	7054	1	0	0
T3	29998	1	0	0
T4	7359	1	0	0
T5	24330	8	0	0
T6	15173	1	0	0
T7	12783	1	0	0
T8	13107	1	0	0
T9	8929	1	0	0
T10	10642	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696262	259	0	0
T18	4583	1	0	0
T19	5451	0	0	0
T20	4628	0	0	0
T22	572	0	0	0
T30	200	0	0	0
T31	224	0	0	0
T32	682	0	0	0
T33	18237	4	0	0
T43	1088	0	0	0
T51	0	1	0	0
T58	0	11	0	0
T96	0	2	0	0
T97	0	3	0	0
T98	0	1	0	0
T99	0	2	0	0
T100	0	5	0	0
T101	0	1	0	0
T131	199	0	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696262	8938	0	0
T1	730	8	0	0
T2	211	1	0	0
T3	898	1	0	0
T4	219	1	0	0
T5	732	8	0	0
T6	453	1	0	0
T7	383	1	0	0
T8	392	1	0	0
T9	266	1	0	0
T10	318	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	22551	0	0
T1	5478	8	0	0
T2	1625	1	0	0
T3	7108	1	0	0
T4	1698	1	0	0
T5	5294	8	0	0
T6	3622	1	0	0
T7	3001	1	0	0
T8	3078	1	0	0
T9	2123	1	0	0
T10	2360	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	22551	0	0
T1	5478	8	0	0
T2	1625	1	0	0
T3	7108	1	0	0
T4	1698	1	0	0
T5	5294	8	0	0
T6	3622	1	0	0
T7	3001	1	0	0
T8	3078	1	0	0
T9	2123	1	0	0
T10	2360	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	22551	0	0
T1	5478	8	0	0
T2	1625	1	0	0
T3	7108	1	0	0
T4	1698	1	0	0
T5	5294	8	0	0
T6	3622	1	0	0
T7	3001	1	0	0
T8	3078	1	0	0
T9	2123	1	0	0
T10	2360	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	22551	0	0
T1	5478	8	0	0
T2	1625	1	0	0
T3	7108	1	0	0
T4	1698	1	0	0
T5	5294	8	0	0
T6	3622	1	0	0
T7	3001	1	0	0
T8	3078	1	0	0
T9	2123	1	0	0
T10	2360	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	22551	0	0
T1	5831	8	0	0
T2	1691	1	0	0
T3	7199	1	0	0
T4	1765	1	0	0
T5	5837	8	0	0
T6	3640	1	0	0
T7	3066	1	0	0
T8	3144	1	0	0
T9	2142	1	0	0
T10	2552	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13426666	22551	0	0
T1	5831	8	0	0
T2	1691	1	0	0
T3	7199	1	0	0
T4	1765	1	0	0
T5	5837	8	0	0
T6	3640	1	0	0
T7	3066	1	0	0
T8	3144	1	0	0
T9	2142	1	0	0
T10	2552	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	22551	0	0
T1	5478	8	0	0
T2	1625	1	0	0
T3	7108	1	0	0
T4	1698	1	0	0
T5	5294	8	0	0
T6	3622	1	0	0
T7	3001	1	0	0
T8	3078	1	0	0
T9	2123	1	0	0
T10	2360	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	22551	0	0
T1	5478	8	0	0
T2	1625	1	0	0
T3	7108	1	0	0
T4	1698	1	0	0
T5	5294	8	0	0
T6	3622	1	0	0
T7	3001	1	0	0
T8	3078	1	0	0
T9	2123	1	0	0
T10	2360	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	22551	0	0
T1	5478	8	0	0
T2	1625	1	0	0
T3	7108	1	0	0
T4	1698	1	0	0
T5	5294	8	0	0
T6	3622	1	0	0
T7	3001	1	0	0
T8	3078	1	0	0
T9	2123	1	0	0
T10	2360	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11921101	22551	0	0
T1	5478	8	0	0
T2	1625	1	0	0
T3	7108	1	0	0
T4	1698	1	0	0
T5	5294	8	0	0
T6	3622	1	0	0
T7	3001	1	0	0
T8	3078	1	0	0
T9	2123	1	0	0
T10	2360	6	0	0