Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	613032	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

368268

1

T1

842

T2

63

T3

975

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	523300	1			T1	1291		T2	99		T3	1411
values[0x0]	228700	1			T1	517		T2	58		T3	584
values[0x1]	229300	1			T1	487		T2	55		T3	596

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	514714	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

466586

1

T1

1064

T2

85

T3

1235

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4526	1			T1	4		T3	12		T5	7
valid_sources[0x01]	5475	1			T1	5		T3	13		T5	16
valid_sources[0x02]	6923	1			T1	5		T3	8		T5	12
valid_sources[0x03]	4158	1			T1	18		T3	8		T5	10
valid_sources[0x04]	2928	1			T1	10		T2	4		T3	15
valid_sources[0x05]	6172	1			T1	12		T2	1		T3	8
valid_sources[0x06]	4378	1			T1	12		T3	9		T5	10
valid_sources[0x07]	3413	1			T1	9		T2	1		T3	7
valid_sources[0x08]	3930	1			T1	4		T3	9		T5	15
valid_sources[0x09]	4138	1			T1	8		T3	18		T5	13
valid_sources[0x0a]	3338	1			T1	5		T3	6		T5	13
valid_sources[0x0b]	4885	1			T1	15		T2	3		T3	11
valid_sources[0x0c]	3449	1			T1	3		T3	15		T5	12
valid_sources[0x0d]	4246	1			T1	6		T3	6		T5	17
valid_sources[0x0e]	3391	1			T1	15		T2	3		T3	7
valid_sources[0x0f]	4837	1			T1	9		T2	4		T3	6
valid_sources[0x10]	3032	1			T1	4		T2	1		T3	11
valid_sources[0x11]	3157	1			T1	7		T3	9		T5	17
valid_sources[0x12]	6145	1			T1	7		T3	13		T5	9
valid_sources[0x13]	2851	1			T1	6		T2	4		T3	19
valid_sources[0x14]	3236	1			T1	15		T2	2		T3	8
valid_sources[0x15]	3220	1			T1	19		T3	10		T5	14
valid_sources[0x16]	4133	1			T1	9		T3	9		T5	18
valid_sources[0x17]	3395	1			T1	16		T3	4		T5	11
valid_sources[0x18]	3131	1			T1	3		T2	1		T3	11
valid_sources[0x19]	4554	1			T1	10		T3	12		T5	15
valid_sources[0x1a]	4339	1			T1	9		T3	12		T5	16
valid_sources[0x1b]	3402	1			T1	6		T2	1		T3	6
valid_sources[0x1c]	4422	1			T1	12		T2	3		T3	14
valid_sources[0x1d]	3438	1			T1	3		T3	16		T5	15
valid_sources[0x1e]	3906	1			T1	7		T3	15		T5	10
valid_sources[0x1f]	3835	1			T1	6		T2	2		T3	8
valid_sources[0x20]	3526	1			T1	6		T3	9		T5	12
valid_sources[0x21]	3524	1			T3	6		T5	14		T8	3
valid_sources[0x22]	3377	1			T1	2		T2	1		T3	10
valid_sources[0x23]	6927	1			T1	13		T3	8		T5	8
valid_sources[0x24]	3050	1			T1	11		T3	9		T5	20
valid_sources[0x25]	3276	1			T1	5		T3	3		T5	15
valid_sources[0x26]	4207	1			T1	4		T2	1		T3	5
valid_sources[0x27]	3733	1			T1	8		T2	2		T3	9
valid_sources[0x28]	3843	1			T1	8		T3	11		T5	15
valid_sources[0x29]	3400	1			T1	7		T2	1		T3	16
valid_sources[0x2a]	3517	1			T1	9		T2	2		T3	10
valid_sources[0x2b]	4668	1			T1	3		T3	15		T5	8
valid_sources[0x2c]	3561	1			T1	3		T2	1		T3	7
valid_sources[0x2d]	4393	1			T1	1		T2	3		T3	13
valid_sources[0x2e]	5072	1			T1	18		T3	13		T5	20
valid_sources[0x2f]	2707	1			T1	16		T3	12		T5	14
valid_sources[0x30]	2936	1			T1	6		T2	1		T3	7
valid_sources[0x31]	3385	1			T1	27		T3	12		T5	10
valid_sources[0x32]	3412	1			T1	5		T2	1		T3	11
valid_sources[0x33]	2803	1			T1	10		T2	2		T3	11
valid_sources[0x34]	2797	1			T1	14		T2	1		T3	13
valid_sources[0x35]	3206	1			T1	17		T2	3		T3	17
valid_sources[0x36]	2891	1			T1	19		T3	8		T5	8
valid_sources[0x37]	3372	1			T1	5		T2	2		T3	8
valid_sources[0x38]	3648	1			T1	5		T3	10		T5	9
valid_sources[0x39]	10556	1			T1	14		T3	12		T5	15
valid_sources[0x3a]	3186	1			T1	2		T3	17		T5	14
valid_sources[0x3b]	4269	1			T1	25		T2	1		T3	14
valid_sources[0x3c]	4088	1			T1	12		T2	1		T3	12
valid_sources[0x3d]	3864	1			T1	8		T3	7		T5	15
valid_sources[0x3e]	3448	1			T1	7		T3	10		T5	12
valid_sources[0x3f]	3292	1			T1	12		T2	2		T3	8
valid_sources[0x40]	3047	1			T1	11		T2	1		T3	5
valid_sources[0x41]	3003	1			T1	4		T2	2		T3	14
valid_sources[0x42]	3570	1			T1	3		T2	1		T3	20
valid_sources[0x43]	3380	1			T1	8		T3	10		T5	7
valid_sources[0x44]	4433	1			T1	14		T3	14		T5	9
valid_sources[0x45]	3569	1			T1	4		T2	1		T3	15
valid_sources[0x46]	3911	1			T1	13		T3	12		T5	17
valid_sources[0x47]	3562	1			T1	2		T3	10		T5	14
valid_sources[0x48]	4864	1			T1	7		T2	1		T3	11
valid_sources[0x49]	6561	1			T1	18		T3	13		T5	10
valid_sources[0x4a]	3704	1			T1	9		T3	10		T5	14
valid_sources[0x4b]	3727	1			T1	14		T2	1		T3	8
valid_sources[0x4c]	4182	1			T1	3		T2	3		T3	8
valid_sources[0x4d]	5799	1			T1	8		T2	1		T3	17
valid_sources[0x4e]	5081	1			T1	13		T2	6		T3	9
valid_sources[0x4f]	3699	1			T1	13		T3	14		T5	18
valid_sources[0x50]	4247	1			T1	5		T3	7		T5	9
valid_sources[0x51]	2753	1			T1	9		T2	3		T3	3
valid_sources[0x52]	4239	1			T1	3		T3	11		T5	12
valid_sources[0x53]	4662	1			T1	7		T3	11		T5	19
valid_sources[0x54]	4247	1			T1	13		T3	9		T5	19
valid_sources[0x55]	4657	1			T1	3		T2	3		T3	8
valid_sources[0x56]	3404	1			T1	24		T3	15		T5	12
valid_sources[0x57]	3920	1			T1	5		T2	1		T3	2
valid_sources[0x58]	3546	1			T1	9		T3	18		T5	16
valid_sources[0x59]	2969	1			T1	1		T3	11		T5	3
valid_sources[0x5a]	3531	1			T1	5		T2	1		T3	11
valid_sources[0x5b]	3133	1			T1	17		T3	7		T5	10
valid_sources[0x5c]	3640	1			T1	22		T2	1		T3	10
valid_sources[0x5d]	3370	1			T1	16		T2	5		T3	4
valid_sources[0x5e]	3564	1			T3	11		T5	11		T9	33
valid_sources[0x5f]	3279	1			T1	20		T3	7		T5	13
valid_sources[0x60]	3332	1			T1	9		T3	6		T5	17
valid_sources[0x61]	3925	1			T1	11		T3	13		T5	14
valid_sources[0x62]	3287	1			T1	19		T3	8		T5	13
valid_sources[0x63]	3489	1			T1	4		T3	8		T5	17
valid_sources[0x64]	3345	1			T1	11		T2	3		T3	7
valid_sources[0x65]	2977	1			T1	5		T3	8		T5	10
valid_sources[0x66]	3358	1			T1	10		T2	3		T3	15
valid_sources[0x67]	2956	1			T1	6		T2	1		T3	6
valid_sources[0x68]	5114	1			T1	9		T2	3		T3	10
valid_sources[0x69]	3357	1			T1	17		T2	2		T3	9
valid_sources[0x6a]	3841	1			T1	10		T3	2		T5	15
valid_sources[0x6b]	3816	1			T1	6		T2	4		T3	12
valid_sources[0x6c]	5549	1			T1	5		T3	9		T5	14
valid_sources[0x6d]	2999	1			T2	3		T3	8		T5	7
valid_sources[0x6e]	6027	1			T1	3		T3	15		T5	21
valid_sources[0x6f]	2760	1			T1	16		T3	11		T5	14
valid_sources[0x70]	3895	1			T1	4		T2	1		T3	13
valid_sources[0x71]	3882	1			T1	10		T3	8		T5	5
valid_sources[0x72]	4333	1			T1	4		T3	13		T5	12
valid_sources[0x73]	4131	1			T1	4		T3	11		T5	9
valid_sources[0x74]	3647	1			T1	13		T2	2		T3	26
valid_sources[0x75]	3127	1			T1	6		T3	8		T5	10
valid_sources[0x76]	3299	1			T1	14		T2	2		T3	8
valid_sources[0x77]	4181	1			T1	5		T3	12		T5	15
valid_sources[0x78]	3128	1			T1	19		T2	1		T3	7
valid_sources[0x79]	3673	1			T1	5		T2	1		T3	8
valid_sources[0x7a]	3571	1			T1	18		T3	10		T5	12
valid_sources[0x7b]	3499	1			T1	14		T3	13		T5	15
valid_sources[0x7c]	2801	1			T1	12		T2	4		T3	1
valid_sources[0x7d]	3501	1			T1	9		T3	12		T5	9
valid_sources[0x7e]	3495	1			T1	13		T3	7		T5	8
valid_sources[0x7f]	3422	1			T1	5		T2	3		T3	16
valid_sources[0x80]	3058	1			T1	8		T3	5		T5	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

245638

1

T1

582

T2

43

T3

656

values[0x0]

all_enables

biggest_size

79855

1

T1

168

T2

14

T3

223

values[0x1]

all_enables

biggest_size

42775

1

T1

92

T2

6

T3

96