Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T23
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T23
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T23
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T23
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T23
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T11
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12595694	13900	0	0
gen_assertions[0].RstEnOn_A	12595694	1171	0	0
gen_assertions[0].RstNOff_A	12595694	13900	0	0
gen_assertions[0].RstNOn_A	12595694	1171	0	0
gen_assertions[1].RstEnOff_A	50382648	12671	0	0
gen_assertions[1].RstEnOn_A	50382648	1161	0	0
gen_assertions[1].RstNOff_A	50382648	12671	0	0
gen_assertions[1].RstNOn_A	50382648	1161	0	0
gen_assertions[2].RstEnOff_A	25192067	12698	0	0
gen_assertions[2].RstEnOn_A	25192067	1125	0	0
gen_assertions[2].RstNOff_A	25192067	12698	0	0
gen_assertions[2].RstNOn_A	25192067	1125	0	0
gen_assertions[3].RstEnOff_A	25191965	12780	0	0
gen_assertions[3].RstEnOn_A	25191965	1209	0	0
gen_assertions[3].RstNOff_A	25191965	12780	0	0
gen_assertions[3].RstNOn_A	25191965	1209	0	0
gen_assertions[4].RstEnOff_A	1590018	21288	0	0
gen_assertions[4].RstEnOn_A	1590018	1227	0	0
gen_assertions[4].RstNOff_A	1590018	21288	0	0
gen_assertions[4].RstNOn_A	1590018	1227	0	0
gen_assertions[5].RstEnOff_A	12595694	14134	0	0
gen_assertions[5].RstEnOn_A	12595694	1271	0	0
gen_assertions[5].RstNOff_A	12595694	14134	0	0
gen_assertions[5].RstNOn_A	12595694	1271	0	0
gen_assertions[6].RstEnOff_A	12595694	14181	0	0
gen_assertions[6].RstEnOn_A	12595694	1316	0	0
gen_assertions[6].RstNOff_A	12595694	14181	0	0
gen_assertions[6].RstNOn_A	12595694	1316	0	0
gen_assertions[7].RstEnOff_A	12595694	14231	0	0
gen_assertions[7].RstEnOn_A	12595694	1369	0	0
gen_assertions[7].RstNOff_A	12595694	14231	0	0
gen_assertions[7].RstNOn_A	12595694	1369	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	13900	0	0
T1	29255	29	0	0
T2	4221	4	0	0
T3	19560	38	0	0
T4	4820	5	0	0
T5	29347	75	0	0
T6	5829	0	0	0
T7	115929	193	0	0
T8	3829	4	0	0
T9	29322	75	0	0
T10	4110	0	0	0
T11	0	234	0	0
T21	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	1171	0	0
T4	4820	1	0	0
T5	29347	0	0	0
T6	5829	0	0	0
T7	115929	27	0	0
T8	3829	0	0	0
T9	29322	0	0	0
T10	4110	0	0	0
T11	288766	21	0	0
T21	2434	0	0	0
T22	5834	0	0	0
T23	0	5	0	0
T45	0	18	0	0
T55	0	8	0	0
T56	0	6	0	0
T73	0	11	0	0
T75	0	1	0	0
T79	0	26	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	13900	0	0
T1	29255	29	0	0
T2	4221	4	0	0
T3	19560	38	0	0
T4	4820	5	0	0
T5	29347	75	0	0
T6	5829	0	0	0
T7	115929	193	0	0
T8	3829	4	0	0
T9	29322	75	0	0
T10	4110	0	0	0
T11	0	234	0	0
T21	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	1171	0	0
T4	4820	1	0	0
T5	29347	0	0	0
T6	5829	0	0	0
T7	115929	27	0	0
T8	3829	0	0	0
T9	29322	0	0	0
T10	4110	0	0	0
T11	288766	21	0	0
T21	2434	0	0	0
T22	5834	0	0	0
T23	0	5	0	0
T45	0	18	0	0
T55	0	8	0	0
T56	0	6	0	0
T73	0	11	0	0
T75	0	1	0	0
T79	0	26	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50382648	12671	0	0
T1	117013	26	0	0
T2	16891	4	0	0
T3	78234	34	0	0
T4	19288	4	0	0
T5	117409	66	0	0
T6	23311	0	0	0
T7	463726	182	0	0
T8	15323	3	0	0
T9	117272	71	0	0
T10	16441	0	0	0
T11	0	215	0	0
T21	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50382648	1161	0	0
T7	463726	36	0	0
T8	15323	0	0	0
T9	117272	0	0	0
T10	16441	0	0	0
T11	115503	20	0	0
T12	21358	0	0	0
T21	9743	0	0	0
T22	23332	0	0	0
T23	13515	6	0	0
T24	9778	0	0	0
T45	0	21	0	0
T55	0	9	0	0
T56	0	8	0	0
T73	0	14	0	0
T79	0	27	0	0
T80	0	15	0	0
T81	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50382648	12671	0	0
T1	117013	26	0	0
T2	16891	4	0	0
T3	78234	34	0	0
T4	19288	4	0	0
T5	117409	66	0	0
T6	23311	0	0	0
T7	463726	182	0	0
T8	15323	3	0	0
T9	117272	71	0	0
T10	16441	0	0	0
T11	0	215	0	0
T21	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50382648	1161	0	0
T7	463726	36	0	0
T8	15323	0	0	0
T9	117272	0	0	0
T10	16441	0	0	0
T11	115503	20	0	0
T12	21358	0	0	0
T21	9743	0	0	0
T22	23332	0	0	0
T23	13515	6	0	0
T24	9778	0	0	0
T45	0	21	0	0
T55	0	9	0	0
T56	0	8	0	0
T73	0	14	0	0
T79	0	27	0	0
T80	0	15	0	0
T81	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25192067	12698	0	0
T1	58515	26	0	0
T2	8443	4	0	0
T3	39126	34	0	0
T4	9640	4	0	0
T5	58682	66	0	0
T6	11652	0	0	0
T7	231859	183	0	0
T8	7663	3	0	0
T9	58646	71	0	0
T10	8220	0	0	0
T11	0	217	0	0
T21	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25192067	1125	0	0
T7	231859	38	0	0
T8	7663	0	0	0
T9	58646	0	0	0
T10	8220	0	0	0
T11	577519	21	0	0
T12	10680	0	0	0
T21	4868	0	0	0
T22	11666	0	0	0
T23	6758	7	0	0
T24	4888	0	0	0
T45	0	20	0	0
T55	0	7	0	0
T56	0	8	0	0
T73	0	12	0	0
T76	0	1	0	0
T79	0	29	0	0
T80	0	17	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25192067	12698	0	0
T1	58515	26	0	0
T2	8443	4	0	0
T3	39126	34	0	0
T4	9640	4	0	0
T5	58682	66	0	0
T6	11652	0	0	0
T7	231859	183	0	0
T8	7663	3	0	0
T9	58646	71	0	0
T10	8220	0	0	0
T11	0	217	0	0
T21	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25192067	1125	0	0
T7	231859	38	0	0
T8	7663	0	0	0
T9	58646	0	0	0
T10	8220	0	0	0
T11	577519	21	0	0
T12	10680	0	0	0
T21	4868	0	0	0
T22	11666	0	0	0
T23	6758	7	0	0
T24	4888	0	0	0
T45	0	20	0	0
T55	0	7	0	0
T56	0	8	0	0
T73	0	12	0	0
T76	0	1	0	0
T79	0	29	0	0
T80	0	17	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25191965	12780	0	0
T1	58522	26	0	0
T2	8442	4	0	0
T3	39127	34	0	0
T4	9641	4	0	0
T5	58709	66	0	0
T6	11659	0	0	0
T7	231889	181	0	0
T8	7661	3	0	0
T9	58636	71	0	0
T10	8220	0	0	0
T11	0	217	0	0
T21	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25191965	1209	0	0
T7	231889	35	0	0
T8	7661	0	0	0
T9	58636	0	0	0
T10	8220	0	0	0
T11	577543	22	0	0
T12	10680	0	0	0
T21	4871	0	0	0
T22	11671	0	0	0
T23	6758	8	0	0
T24	4891	0	0	0
T45	0	21	0	0
T55	0	10	0	0
T56	0	8	0	0
T73	0	12	0	0
T79	0	31	0	0
T80	0	18	0	0
T82	0	4	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25191965	12780	0	0
T1	58522	26	0	0
T2	8442	4	0	0
T3	39127	34	0	0
T4	9641	4	0	0
T5	58709	66	0	0
T6	11659	0	0	0
T7	231889	181	0	0
T8	7661	3	0	0
T9	58636	71	0	0
T10	8220	0	0	0
T11	0	217	0	0
T21	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25191965	1209	0	0
T7	231889	35	0	0
T8	7661	0	0	0
T9	58636	0	0	0
T10	8220	0	0	0
T11	577543	22	0	0
T12	10680	0	0	0
T21	4871	0	0	0
T22	11671	0	0	0
T23	6758	8	0	0
T24	4891	0	0	0
T45	0	21	0	0
T55	0	10	0	0
T56	0	8	0	0
T73	0	12	0	0
T79	0	31	0	0
T80	0	18	0	0
T82	0	4	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590018	21288	0	0
T1	3701	44	0	0
T2	527	6	0	0
T3	2505	53	0	0
T4	601	7	0	0
T5	3683	75	0	0
T6	729	3	0	0
T7	14810	287	0	0
T8	478	6	0	0
T9	3680	77	0	0
T10	512	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590018	1227	0	0
T4	601	1	0	0
T5	3683	0	0	0
T6	729	0	0	0
T7	14810	35	0	0
T8	478	0	0	0
T9	3680	0	0	0
T10	512	0	0	0
T11	36449	23	0	0
T21	304	0	0	0
T22	731	0	0	0
T23	0	10	0	0
T41	0	1	0	0
T45	0	22	0	0
T55	0	12	0	0
T56	0	9	0	0
T73	0	8	0	0
T79	0	26	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590018	21288	0	0
T1	3701	44	0	0
T2	527	6	0	0
T3	2505	53	0	0
T4	601	7	0	0
T5	3683	75	0	0
T6	729	3	0	0
T7	14810	287	0	0
T8	478	6	0	0
T9	3680	77	0	0
T10	512	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590018	1227	0	0
T4	601	1	0	0
T5	3683	0	0	0
T6	729	0	0	0
T7	14810	35	0	0
T8	478	0	0	0
T9	3680	0	0	0
T10	512	0	0	0
T11	36449	23	0	0
T21	304	0	0	0
T22	731	0	0	0
T23	0	10	0	0
T41	0	1	0	0
T45	0	22	0	0
T55	0	12	0	0
T56	0	9	0	0
T73	0	8	0	0
T79	0	26	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	14134	0	0
T1	29255	29	0	0
T2	4221	4	0	0
T3	19560	38	0	0
T4	4820	4	0	0
T5	29347	75	0	0
T6	5829	0	0	0
T7	115929	202	0	0
T8	3829	4	0	0
T9	29322	75	0	0
T10	4110	0	0	0
T11	0	232	0	0
T21	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	1271	0	0
T7	115929	36	0	0
T8	3829	0	0	0
T9	29322	0	0	0
T10	4110	0	0	0
T11	288766	17	0	0
T12	5339	0	0	0
T21	2434	0	0	0
T22	5834	0	0	0
T23	3378	11	0	0
T24	2443	0	0	0
T45	0	24	0	0
T55	0	12	0	0
T56	0	9	0	0
T73	0	10	0	0
T79	0	24	0	0
T80	0	17	0	0
T82	0	7	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	14134	0	0
T1	29255	29	0	0
T2	4221	4	0	0
T3	19560	38	0	0
T4	4820	4	0	0
T5	29347	75	0	0
T6	5829	0	0	0
T7	115929	202	0	0
T8	3829	4	0	0
T9	29322	75	0	0
T10	4110	0	0	0
T11	0	232	0	0
T21	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	1271	0	0
T7	115929	36	0	0
T8	3829	0	0	0
T9	29322	0	0	0
T10	4110	0	0	0
T11	288766	17	0	0
T12	5339	0	0	0
T21	2434	0	0	0
T22	5834	0	0	0
T23	3378	11	0	0
T24	2443	0	0	0
T45	0	24	0	0
T55	0	12	0	0
T56	0	9	0	0
T73	0	10	0	0
T79	0	24	0	0
T80	0	17	0	0
T82	0	7	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	14181	0	0
T1	29255	29	0	0
T2	4221	4	0	0
T3	19560	38	0	0
T4	4820	4	0	0
T5	29347	75	0	0
T6	5829	0	0	0
T7	115929	201	0	0
T8	3829	4	0	0
T9	29322	75	0	0
T10	4110	0	0	0
T11	0	235	0	0
T21	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	1316	0	0
T7	115929	36	0	0
T8	3829	0	0	0
T9	29322	0	0	0
T10	4110	0	0	0
T11	288766	21	0	0
T12	5339	0	0	0
T21	2434	0	0	0
T22	5834	0	0	0
T23	3378	10	0	0
T24	2443	0	0	0
T45	0	18	0	0
T55	0	10	0	0
T56	0	10	0	0
T73	0	8	0	0
T79	0	28	0	0
T80	0	13	0	0
T82	0	8	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	14181	0	0
T1	29255	29	0	0
T2	4221	4	0	0
T3	19560	38	0	0
T4	4820	4	0	0
T5	29347	75	0	0
T6	5829	0	0	0
T7	115929	201	0	0
T8	3829	4	0	0
T9	29322	75	0	0
T10	4110	0	0	0
T11	0	235	0	0
T21	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	1316	0	0
T7	115929	36	0	0
T8	3829	0	0	0
T9	29322	0	0	0
T10	4110	0	0	0
T11	288766	21	0	0
T12	5339	0	0	0
T21	2434	0	0	0
T22	5834	0	0	0
T23	3378	10	0	0
T24	2443	0	0	0
T45	0	18	0	0
T55	0	10	0	0
T56	0	10	0	0
T73	0	8	0	0
T79	0	28	0	0
T80	0	13	0	0
T82	0	8	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	14231	0	0
T1	29255	29	0	0
T2	4221	4	0	0
T3	19560	38	0	0
T4	4820	5	0	0
T5	29347	75	0	0
T6	5829	0	0	0
T7	115929	201	0	0
T8	3829	4	0	0
T9	29322	75	0	0
T10	4110	0	0	0
T11	0	239	0	0
T21	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	1369	0	0
T4	4820	1	0	0
T5	29347	0	0	0
T6	5829	0	0	0
T7	115929	37	0	0
T8	3829	0	0	0
T9	29322	0	0	0
T10	4110	0	0	0
T11	288766	25	0	0
T21	2434	0	0	0
T22	5834	0	0	0
T23	0	11	0	0
T45	0	21	0	0
T55	0	13	0	0
T56	0	13	0	0
T73	0	10	0	0
T79	0	27	0	0
T80	0	15	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	14231	0	0
T1	29255	29	0	0
T2	4221	4	0	0
T3	19560	38	0	0
T4	4820	5	0	0
T5	29347	75	0	0
T6	5829	0	0	0
T7	115929	201	0	0
T8	3829	4	0	0
T9	29322	75	0	0
T10	4110	0	0	0
T11	0	239	0	0
T21	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	1369	0	0
T4	4820	1	0	0
T5	29347	0	0	0
T6	5829	0	0	0
T7	115929	37	0	0
T8	3829	0	0	0
T9	29322	0	0	0
T10	4110	0	0	0
T11	288766	25	0	0
T21	2434	0	0	0
T22	5834	0	0	0
T23	0	11	0	0
T45	0	21	0	0
T55	0	13	0	0
T56	0	13	0	0
T73	0	10	0	0
T79	0	27	0	0
T80	0	15	0	0