Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11967800	8971	0	0
alert_regwen_rd_A	11967800	5181	0	0
cpu_regwen_rd_A	11967800	5288	0	0
sw_rst_ctrl_n_0_rd_A	11967800	9827	0	0
sw_rst_ctrl_n_1_rd_A	11967800	9956	0	0
sw_rst_ctrl_n_2_rd_A	11967800	9948	0	0
sw_rst_ctrl_n_3_rd_A	11967800	9582	0	0
sw_rst_ctrl_n_4_rd_A	11967800	9961	0	0
sw_rst_ctrl_n_5_rd_A	11967800	9943	0	0
sw_rst_ctrl_n_6_rd_A	11967800	9744	0	0
sw_rst_ctrl_n_7_rd_A	11967800	9905	0	0
sw_rst_regwen_0_rd_A	11967800	5568	0	0
sw_rst_regwen_1_rd_A	11967800	5623	0	0
sw_rst_regwen_2_rd_A	11967800	5632	0	0
sw_rst_regwen_3_rd_A	11967800	5846	0	0
sw_rst_regwen_4_rd_A	11967800	5697	0	0
sw_rst_regwen_5_rd_A	11967800	5582	0	0
sw_rst_regwen_6_rd_A	11967800	5793	0	0
sw_rst_regwen_7_rd_A	11967800	5773	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	8971	0	0
T58	18787	1	0	0
T61	4697	15	0	0
T62	2922	10	0	0
T63	3207	8	0	0
T64	9838	422	0	0
T83	4221	65	0	0
T84	10699	624	0	0
T85	16320	942	0	0
T86	2827	4	0	0
T87	3453	191	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	5181	0	0
T11	258583	340	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	37	0	0
T46	42165	0	0	0
T80	0	442	0	0
T91	0	68	0	0
T96	0	259	0	0
T98	0	120	0	0
T99	0	83	0	0
T116	0	42	0	0
T117	0	199	0	0
T118	0	228	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	5288	0	0
T11	258583	396	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	28	0	0
T46	42165	0	0	0
T80	0	383	0	0
T91	0	52	0	0
T96	0	237	0	0
T98	0	120	0	0
T99	0	101	0	0
T116	0	66	0	0
T117	0	283	0	0
T118	0	227	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	9827	0	0
T11	258583	649	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	36	0	0
T40	0	20	0	0
T46	42165	0	0	0
T55	0	218	0	0
T56	0	200	0	0
T73	0	138	0	0
T78	0	19	0	0
T80	0	580	0	0
T82	0	113	0	0
T91	0	64	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	9956	0	0
T11	258583	629	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	23	0	0
T40	0	12	0	0
T46	42165	0	0	0
T55	0	220	0	0
T56	0	191	0	0
T73	0	166	0	0
T78	0	5	0	0
T80	0	618	0	0
T82	0	157	0	0
T91	0	60	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	9948	0	0
T11	258583	674	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	28	0	0
T40	0	5	0	0
T46	42165	0	0	0
T55	0	195	0	0
T56	0	181	0	0
T73	0	151	0	0
T78	0	21	0	0
T80	0	595	0	0
T82	0	149	0	0
T91	0	62	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	9582	0	0
T11	258583	657	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	39	0	0
T40	0	16	0	0
T46	42165	0	0	0
T55	0	226	0	0
T56	0	160	0	0
T73	0	124	0	0
T78	0	10	0	0
T80	0	595	0	0
T82	0	140	0	0
T91	0	49	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	9961	0	0
T11	258583	651	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	35	0	0
T40	0	11	0	0
T46	42165	0	0	0
T55	0	189	0	0
T56	0	190	0	0
T73	0	159	0	0
T78	0	3	0	0
T80	0	653	0	0
T82	0	147	0	0
T91	0	47	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	9943	0	0
T11	258583	692	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	39	0	0
T40	0	42	0	0
T46	42165	0	0	0
T55	0	204	0	0
T56	0	239	0	0
T73	0	153	0	0
T78	0	14	0	0
T80	0	647	0	0
T82	0	147	0	0
T91	0	46	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	9744	0	0
T11	258583	597	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	41	0	0
T40	0	19	0	0
T46	42165	0	0	0
T55	0	168	0	0
T56	0	215	0	0
T73	0	128	0	0
T78	0	7	0	0
T80	0	638	0	0
T82	0	118	0	0
T91	0	45	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	9905	0	0
T11	258583	658	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	26	0	0
T40	0	18	0	0
T46	42165	0	0	0
T55	0	186	0	0
T56	0	225	0	0
T73	0	165	0	0
T78	0	10	0	0
T80	0	647	0	0
T82	0	150	0	0
T91	0	63	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	5568	0	0
T11	258583	371	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	27	0	0
T46	42165	0	0	0
T55	0	28	0	0
T56	0	15	0	0
T80	0	493	0	0
T82	0	32	0	0
T91	0	83	0	0
T96	0	207	0	0
T99	0	84	0	0
T119	0	7	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	5623	0	0
T11	258583	413	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	39	0	0
T46	42165	0	0	0
T55	0	35	0	0
T56	0	30	0	0
T80	0	399	0	0
T82	0	34	0	0
T91	0	66	0	0
T96	0	239	0	0
T99	0	68	0	0
T119	0	15	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	5632	0	0
T11	258583	410	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	40	0	0
T46	42165	0	0	0
T55	0	29	0	0
T56	0	42	0	0
T80	0	415	0	0
T82	0	26	0	0
T91	0	68	0	0
T96	0	194	0	0
T99	0	88	0	0
T119	0	8	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	5846	0	0
T11	258583	369	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	30	0	0
T46	42165	0	0	0
T55	0	38	0	0
T56	0	24	0	0
T80	0	421	0	0
T82	0	39	0	0
T91	0	60	0	0
T96	0	273	0	0
T99	0	71	0	0
T119	0	5	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	5697	0	0
T11	258583	343	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	27	0	0
T46	42165	0	0	0
T55	0	16	0	0
T56	0	42	0	0
T80	0	391	0	0
T82	0	29	0	0
T91	0	47	0	0
T96	0	230	0	0
T99	0	79	0	0
T119	0	4	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	5582	0	0
T11	258583	328	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	24	0	0
T46	42165	0	0	0
T55	0	18	0	0
T56	0	33	0	0
T80	0	416	0	0
T82	0	36	0	0
T91	0	62	0	0
T96	0	221	0	0
T99	0	95	0	0
T119	0	11	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	5793	0	0
T11	258583	396	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	34	0	0
T46	42165	0	0	0
T55	0	31	0	0
T56	0	35	0	0
T80	0	407	0	0
T82	0	27	0	0
T91	0	53	0	0
T96	0	227	0	0
T99	0	90	0	0
T120	0	30	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11967800	5773	0	0
T11	258583	359	0	0
T12	5224	0	0	0
T13	4293	0	0	0
T21	2102	0	0	0
T22	5096	0	0	0
T23	3311	0	0	0
T24	2253	0	0	0
T25	31489	0	0	0
T26	34379	28	0	0
T46	42165	0	0	0
T55	0	35	0	0
T56	0	36	0	0
T80	0	426	0	0
T82	0	24	0	0
T91	0	61	0	0
T96	0	239	0	0
T99	0	94	0	0
T119	0	14	0	0