Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T7

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52483621	8578	0	0
CascadeEffAonToRstPorAboveRise_A	52483621	8578	0	0
CascadeEffAonToRstPorIoAboveFall_A	50382648	8578	0	0
CascadeEffAonToRstPorIoAboveRise_A	50382648	8578	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25192067	8578	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25192067	8578	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12595694	8578	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12595694	8578	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25191965	8578	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25191965	8578	0	0
CascadeLcToLcAboveFall_A	52483621	21475	0	0
CascadeLcToLcAboveRise_A	52483621	21475	0	0
CascadeLcToLcAonAboveFall_A	1590018	21475	0	0
CascadeLcToLcAonAboveRise_A	1590018	21475	0	0
CascadeLcToLcShadowedAboveFall_A	52483621	21475	0	0
CascadeLcToLcShadowedAboveRise_A	52483621	21475	0	0
CascadePorToAonAboveFall_A	1590018	6891	0	0
CascadeSysToSysAboveFall_A	52483621	21475	0	0
CascadeSysToSysAboveRise_A	52483621	21475	0	0
ScanRstToAonRise_A	1590018	215	0	0
StablePorToAonRise_A	1590018	8578	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11130777	21475	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11130777	21475	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11130777	21475	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11130777	21475	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12595694	21475	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12595694	21475	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11130777	21475	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11130777	21475	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11130777	21475	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11130777	21475	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52483621	8578	0	0
T1	121902	16	0	0
T2	17592	2	0	0
T3	81511	15	0	0
T4	20090	2	0	0
T5	122261	27	0	0
T6	24287	8	0	0
T7	483108	96	0	0
T8	15963	2	0	0
T9	122154	27	0	0
T10	17126	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52483621	8578	0	0
T1	121902	16	0	0
T2	17592	2	0	0
T3	81511	15	0	0
T4	20090	2	0	0
T5	122261	27	0	0
T6	24287	8	0	0
T7	483108	96	0	0
T8	15963	2	0	0
T9	122154	27	0	0
T10	17126	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50382648	8578	0	0
T1	117013	16	0	0
T2	16891	2	0	0
T3	78234	15	0	0
T4	19288	2	0	0
T5	117409	27	0	0
T6	23311	8	0	0
T7	463726	96	0	0
T8	15323	2	0	0
T9	117272	27	0	0
T10	16441	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50382648	8578	0	0
T1	117013	16	0	0
T2	16891	2	0	0
T3	78234	15	0	0
T4	19288	2	0	0
T5	117409	27	0	0
T6	23311	8	0	0
T7	463726	96	0	0
T8	15323	2	0	0
T9	117272	27	0	0
T10	16441	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25192067	8578	0	0
T1	58515	16	0	0
T2	8443	2	0	0
T3	39126	15	0	0
T4	9640	2	0	0
T5	58682	27	0	0
T6	11652	8	0	0
T7	231859	96	0	0
T8	7663	2	0	0
T9	58646	27	0	0
T10	8220	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25192067	8578	0	0
T1	58515	16	0	0
T2	8443	2	0	0
T3	39126	15	0	0
T4	9640	2	0	0
T5	58682	27	0	0
T6	11652	8	0	0
T7	231859	96	0	0
T8	7663	2	0	0
T9	58646	27	0	0
T10	8220	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	8578	0	0
T1	29255	16	0	0
T2	4221	2	0	0
T3	19560	15	0	0
T4	4820	2	0	0
T5	29347	27	0	0
T6	5829	8	0	0
T7	115929	96	0	0
T8	3829	2	0	0
T9	29322	27	0	0
T10	4110	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	8578	0	0
T1	29255	16	0	0
T2	4221	2	0	0
T3	19560	15	0	0
T4	4820	2	0	0
T5	29347	27	0	0
T6	5829	8	0	0
T7	115929	96	0	0
T8	3829	2	0	0
T9	29322	27	0	0
T10	4110	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25191965	8578	0	0
T1	58522	16	0	0
T2	8442	2	0	0
T3	39127	15	0	0
T4	9641	2	0	0
T5	58709	27	0	0
T6	11659	8	0	0
T7	231889	96	0	0
T8	7661	2	0	0
T9	58636	27	0	0
T10	8220	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25191965	8578	0	0
T1	58522	16	0	0
T2	8442	2	0	0
T3	39127	15	0	0
T4	9641	2	0	0
T5	58709	27	0	0
T6	11659	8	0	0
T7	231889	96	0	0
T8	7661	2	0	0
T9	58636	27	0	0
T10	8220	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52483621	21475	0	0
T1	121902	45	0	0
T2	17592	6	0	0
T3	81511	53	0	0
T4	20090	6	0	0
T5	122261	102	0	0
T6	24287	8	0	0
T7	483108	263	0	0
T8	15963	6	0	0
T9	122154	102	0	0
T10	17126	2	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52483621	21475	0	0
T1	121902	45	0	0
T2	17592	6	0	0
T3	81511	53	0	0
T4	20090	6	0	0
T5	122261	102	0	0
T6	24287	8	0	0
T7	483108	263	0	0
T8	15963	6	0	0
T9	122154	102	0	0
T10	17126	2	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590018	21475	0	0
T1	3701	45	0	0
T2	527	6	0	0
T3	2505	53	0	0
T4	601	6	0	0
T5	3683	102	0	0
T6	729	8	0	0
T7	14810	263	0	0
T8	478	6	0	0
T9	3680	102	0	0
T10	512	2	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590018	21475	0	0
T1	3701	45	0	0
T2	527	6	0	0
T3	2505	53	0	0
T4	601	6	0	0
T5	3683	102	0	0
T6	729	8	0	0
T7	14810	263	0	0
T8	478	6	0	0
T9	3680	102	0	0
T10	512	2	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52483621	21475	0	0
T1	121902	45	0	0
T2	17592	6	0	0
T3	81511	53	0	0
T4	20090	6	0	0
T5	122261	102	0	0
T6	24287	8	0	0
T7	483108	263	0	0
T8	15963	6	0	0
T9	122154	102	0	0
T10	17126	2	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52483621	21475	0	0
T1	121902	45	0	0
T2	17592	6	0	0
T3	81511	53	0	0
T4	20090	6	0	0
T5	122261	102	0	0
T6	24287	8	0	0
T7	483108	263	0	0
T8	15963	6	0	0
T9	122154	102	0	0
T10	17126	2	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590018	6891	0	0
T1	3701	8	0	0
T2	527	1	0	0
T3	2505	8	0	0
T4	601	1	0	0
T5	3683	27	0	0
T6	729	8	0	0
T7	14810	54	0	0
T8	478	1	0	0
T9	3680	27	0	0
T10	512	11	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52483621	21475	0	0
T1	121902	45	0	0
T2	17592	6	0	0
T3	81511	53	0	0
T4	20090	6	0	0
T5	122261	102	0	0
T6	24287	8	0	0
T7	483108	263	0	0
T8	15963	6	0	0
T9	122154	102	0	0
T10	17126	2	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52483621	21475	0	0
T1	121902	45	0	0
T2	17592	6	0	0
T3	81511	53	0	0
T4	20090	6	0	0
T5	122261	102	0	0
T6	24287	8	0	0
T7	483108	263	0	0
T8	15963	6	0	0
T9	122154	102	0	0
T10	17126	2	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590018	215	0	0
T1	3701	1	0	0
T2	527	0	0	0
T3	2505	1	0	0
T4	601	0	0	0
T5	3683	0	0	0
T6	729	0	0	0
T7	14810	5	0	0
T8	478	0	0	0
T9	3680	0	0	0
T10	512	0	0	0
T11	0	4	0	0
T25	0	3	0	0
T45	0	1	0	0
T79	0	7	0	0
T80	0	8	0	0
T90	0	2	0	0
T99	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590018	8578	0	0
T1	3701	16	0	0
T2	527	2	0	0
T3	2505	15	0	0
T4	601	2	0	0
T5	3683	27	0	0
T6	729	8	0	0
T7	14810	96	0	0
T8	478	2	0	0
T9	3680	27	0	0
T10	512	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11130777	21475	0	0
T1	25152	45	0	0
T2	3981	6	0	0
T3	14474	53	0	0
T4	4530	6	0	0
T5	26019	102	0	0
T6	5475	8	0	0
T7	95283	263	0	0
T8	3590	6	0	0
T9	26103	102	0	0
T10	4019	2	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11130777	21475	0	0
T1	25152	45	0	0
T2	3981	6	0	0
T3	14474	53	0	0
T4	4530	6	0	0
T5	26019	102	0	0
T6	5475	8	0	0
T7	95283	263	0	0
T8	3590	6	0	0
T9	26103	102	0	0
T10	4019	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11130777	21475	0	0
T1	25152	45	0	0
T2	3981	6	0	0
T3	14474	53	0	0
T4	4530	6	0	0
T5	26019	102	0	0
T6	5475	8	0	0
T7	95283	263	0	0
T8	3590	6	0	0
T9	26103	102	0	0
T10	4019	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11130777	21475	0	0
T1	25152	45	0	0
T2	3981	6	0	0
T3	14474	53	0	0
T4	4530	6	0	0
T5	26019	102	0	0
T6	5475	8	0	0
T7	95283	263	0	0
T8	3590	6	0	0
T9	26103	102	0	0
T10	4019	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	21475	0	0
T1	29255	45	0	0
T2	4221	6	0	0
T3	19560	53	0	0
T4	4820	6	0	0
T5	29347	102	0	0
T6	5829	8	0	0
T7	115929	263	0	0
T8	3829	6	0	0
T9	29322	102	0	0
T10	4110	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12595694	21475	0	0
T1	29255	45	0	0
T2	4221	6	0	0
T3	19560	53	0	0
T4	4820	6	0	0
T5	29347	102	0	0
T6	5829	8	0	0
T7	115929	263	0	0
T8	3829	6	0	0
T9	29322	102	0	0
T10	4110	2	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11130777	21475	0	0
T1	25152	45	0	0
T2	3981	6	0	0
T3	14474	53	0	0
T4	4530	6	0	0
T5	26019	102	0	0
T6	5475	8	0	0
T7	95283	263	0	0
T8	3590	6	0	0
T9	26103	102	0	0
T10	4019	2	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11130777	21475	0	0
T1	25152	45	0	0
T2	3981	6	0	0
T3	14474	53	0	0
T4	4530	6	0	0
T5	26019	102	0	0
T6	5475	8	0	0
T7	95283	263	0	0
T8	3590	6	0	0
T9	26103	102	0	0
T10	4019	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11130777	21475	0	0
T1	25152	45	0	0
T2	3981	6	0	0
T3	14474	53	0	0
T4	4530	6	0	0
T5	26019	102	0	0
T6	5475	8	0	0
T7	95283	263	0	0
T8	3590	6	0	0
T9	26103	102	0	0
T10	4019	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11130777	21475	0	0
T1	25152	45	0	0
T2	3981	6	0	0
T3	14474	53	0	0
T4	4530	6	0	0
T5	26019	102	0	0
T6	5475	8	0	0
T7	95283	263	0	0
T8	3590	6	0	0
T9	26103	102	0	0
T10	4019	2	0	0