Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	632935	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

380846

1

T4

4430

T5

4

T6

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	542041	1			T2	1		T3	1		T4	6585
values[0x0]	235018	1			T4	2705		T5	11		T6	8
values[0x1]	236722	1			T4	2818		T5	6		T6	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	530812	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

482969

1

T4

5699

T5

4

T6

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4157	1			T10	33		T13	2		T21	5
valid_sources[0x01]	3723	1			T4	299		T10	27		T22	4
valid_sources[0x02]	3150	1			T10	24		T13	2		T21	1
valid_sources[0x03]	3346	1			T4	113		T10	27		T22	12
valid_sources[0x04]	3973	1			T10	25		T13	1		T22	12
valid_sources[0x05]	3439	1			T10	20		T22	8		T24	68
valid_sources[0x06]	4534	1			T10	28		T13	1		T22	9
valid_sources[0x07]	4582	1			T4	6		T5	1		T10	22
valid_sources[0x08]	3869	1			T10	24		T11	4		T13	3
valid_sources[0x09]	3592	1			T10	24		T13	1		T22	9
valid_sources[0x0a]	4930	1			T10	17		T22	10		T23	1
valid_sources[0x0b]	3975	1			T10	25		T11	1		T13	2
valid_sources[0x0c]	3259	1			T10	20		T11	1		T13	1
valid_sources[0x0d]	3711	1			T10	16		T22	9		T24	50
valid_sources[0x0e]	3918	1			T4	174		T10	20		T22	9
valid_sources[0x0f]	3696	1			T10	19		T13	1		T21	4
valid_sources[0x10]	3256	1			T2	1		T4	13		T10	19
valid_sources[0x11]	3552	1			T10	41		T13	1		T22	15
valid_sources[0x12]	4614	1			T4	539		T10	25		T11	1
valid_sources[0x13]	3255	1			T10	24		T11	4		T13	2
valid_sources[0x14]	3315	1			T10	22		T13	1		T21	1
valid_sources[0x15]	3617	1			T4	413		T10	33		T13	2
valid_sources[0x16]	3812	1			T4	314		T10	28		T11	4
valid_sources[0x17]	3601	1			T10	22		T22	8		T24	75
valid_sources[0x18]	3579	1			T10	25		T21	4		T22	16
valid_sources[0x19]	3616	1			T10	27		T13	1		T22	24
valid_sources[0x1a]	3801	1			T10	22		T13	1		T22	14
valid_sources[0x1b]	4559	1			T4	71		T10	30		T21	2
valid_sources[0x1c]	3300	1			T10	19		T13	1		T22	11
valid_sources[0x1d]	6475	1			T10	27		T13	2		T22	13
valid_sources[0x1e]	3824	1			T10	24		T11	4		T13	1
valid_sources[0x1f]	3566	1			T10	33		T11	1		T13	1
valid_sources[0x20]	3550	1			T10	23		T21	2		T22	13
valid_sources[0x21]	3684	1			T10	24		T22	16		T24	66
valid_sources[0x22]	3610	1			T4	1		T10	23		T13	2
valid_sources[0x23]	4799	1			T10	17		T13	1		T22	13
valid_sources[0x24]	5281	1			T4	316		T10	21		T13	1
valid_sources[0x25]	3034	1			T10	21		T22	12		T23	3
valid_sources[0x26]	3386	1			T10	28		T22	15		T23	7
valid_sources[0x27]	4043	1			T4	448		T6	5		T10	34
valid_sources[0x28]	3880	1			T10	19		T13	2		T22	14
valid_sources[0x29]	3125	1			T4	5		T10	24		T11	1
valid_sources[0x2a]	3325	1			T10	19		T11	1		T13	2
valid_sources[0x2b]	4021	1			T4	167		T10	30		T13	1
valid_sources[0x2c]	4242	1			T4	155		T5	1		T10	32
valid_sources[0x2d]	3656	1			T5	1		T10	27		T22	13
valid_sources[0x2e]	3721	1			T10	21		T11	1		T21	5
valid_sources[0x2f]	3373	1			T10	23		T22	8		T23	2
valid_sources[0x30]	3444	1			T10	18		T13	2		T22	13
valid_sources[0x31]	3694	1			T10	25		T13	2		T21	5
valid_sources[0x32]	4391	1			T4	70		T10	18		T13	1
valid_sources[0x33]	3966	1			T6	1		T10	31		T11	9
valid_sources[0x34]	3861	1			T10	25		T21	22		T22	16
valid_sources[0x35]	3654	1			T4	322		T10	19		T11	3
valid_sources[0x36]	3787	1			T4	320		T10	42		T22	12
valid_sources[0x37]	4111	1			T5	2		T10	31		T11	3
valid_sources[0x38]	3785	1			T4	63		T10	17		T11	2
valid_sources[0x39]	3360	1			T10	22		T11	4		T21	7
valid_sources[0x3a]	3456	1			T4	198		T10	16		T22	6
valid_sources[0x3b]	4223	1			T10	18		T13	2		T22	7
valid_sources[0x3c]	3374	1			T4	145		T10	21		T21	3
valid_sources[0x3d]	3942	1			T4	6		T10	24		T22	6
valid_sources[0x3e]	4290	1			T4	57		T10	25		T13	1
valid_sources[0x3f]	3564	1			T10	30		T22	9		T24	58
valid_sources[0x40]	3910	1			T10	29		T22	10		T24	66
valid_sources[0x41]	3451	1			T10	26		T11	1		T13	2
valid_sources[0x42]	3453	1			T5	1		T10	13		T13	1
valid_sources[0x43]	3567	1			T10	21		T13	2		T22	5
valid_sources[0x44]	3264	1			T10	23		T13	1		T22	16
valid_sources[0x45]	4250	1			T4	303		T10	22		T22	9
valid_sources[0x46]	4495	1			T4	107		T10	26		T13	2
valid_sources[0x47]	3075	1			T10	29		T13	2		T22	16
valid_sources[0x48]	4029	1			T10	26		T22	10		T24	62
valid_sources[0x49]	3990	1			T10	11		T22	5		T23	1
valid_sources[0x4a]	4328	1			T10	19		T13	1		T21	6
valid_sources[0x4b]	3162	1			T10	21		T13	1		T22	13
valid_sources[0x4c]	3871	1			T4	70		T10	24		T13	2
valid_sources[0x4d]	7023	1			T10	17		T22	11		T24	69
valid_sources[0x4e]	3486	1			T10	29		T22	12		T24	49
valid_sources[0x4f]	3442	1			T10	38		T22	18		T24	56
valid_sources[0x50]	4421	1			T10	18		T13	2		T22	15
valid_sources[0x51]	4183	1			T10	17		T22	13		T24	38
valid_sources[0x52]	3584	1			T10	32		T11	1		T22	15
valid_sources[0x53]	3755	1			T4	8		T10	29		T22	15
valid_sources[0x54]	2995	1			T10	24		T13	1		T22	12
valid_sources[0x55]	3174	1			T10	46		T13	2		T22	14
valid_sources[0x56]	4775	1			T10	20		T13	1		T22	16
valid_sources[0x57]	3701	1			T3	1		T10	25		T11	1
valid_sources[0x58]	3684	1			T10	26		T11	1		T22	13
valid_sources[0x59]	3578	1			T10	26		T22	9		T23	2
valid_sources[0x5a]	3926	1			T10	26		T13	1		T22	12
valid_sources[0x5b]	4750	1			T10	25		T22	11		T23	1
valid_sources[0x5c]	3999	1			T10	23		T22	25		T23	3
valid_sources[0x5d]	3870	1			T4	382		T5	1		T10	26
valid_sources[0x5e]	3591	1			T4	5		T10	19		T13	3
valid_sources[0x5f]	4102	1			T5	2		T6	3		T10	35
valid_sources[0x60]	3878	1			T10	22		T11	2		T22	10
valid_sources[0x61]	4419	1			T4	20		T10	23		T11	13
valid_sources[0x62]	4525	1			T4	2		T10	27		T13	2
valid_sources[0x63]	3311	1			T10	24		T11	3		T22	20
valid_sources[0x64]	3802	1			T10	19		T21	11		T22	14
valid_sources[0x65]	4384	1			T10	19		T11	1		T13	2
valid_sources[0x66]	3714	1			T4	268		T10	23		T13	1
valid_sources[0x67]	3766	1			T10	33		T11	10		T22	13
valid_sources[0x68]	3449	1			T10	22		T13	2		T22	21
valid_sources[0x69]	3714	1			T10	25		T11	1		T13	3
valid_sources[0x6a]	4108	1			T10	30		T13	2		T21	2
valid_sources[0x6b]	3687	1			T4	11		T10	27		T11	4
valid_sources[0x6c]	4944	1			T4	4		T10	19		T13	1
valid_sources[0x6d]	3523	1			T10	29		T22	15		T24	51
valid_sources[0x6e]	3977	1			T4	8		T10	18		T13	2
valid_sources[0x6f]	6612	1			T4	5		T10	39		T21	7
valid_sources[0x70]	3505	1			T4	75		T10	22		T11	1
valid_sources[0x71]	3040	1			T4	5		T10	17		T22	13
valid_sources[0x72]	3311	1			T4	2		T10	27		T13	1
valid_sources[0x73]	4485	1			T10	16		T22	11		T24	55
valid_sources[0x74]	4719	1			T4	9		T10	32		T13	1
valid_sources[0x75]	4301	1			T10	19		T11	3		T22	15
valid_sources[0x76]	4170	1			T10	25		T13	1		T22	15
valid_sources[0x77]	3200	1			T10	20		T22	10		T23	1
valid_sources[0x78]	3586	1			T4	140		T10	15		T13	3
valid_sources[0x79]	5097	1			T10	18		T21	11		T22	15
valid_sources[0x7a]	3492	1			T10	29		T22	13		T24	48
valid_sources[0x7b]	3444	1			T4	57		T10	30		T11	2
valid_sources[0x7c]	3953	1			T4	70		T10	32		T13	1
valid_sources[0x7d]	3215	1			T4	4		T10	31		T11	1
valid_sources[0x7e]	3920	1			T6	2		T10	21		T22	18
valid_sources[0x7f]	3280	1			T10	25		T11	4		T22	24
valid_sources[0x80]	3537	1			T10	26		T21	1		T22	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

253690

1

T4

3046

T9

80

T10

1658

values[0x0]

all_enables

biggest_size

82594

1

T4

912

T5

3

T6

1

values[0x1]

all_enables

biggest_size

44562

1

T4

472

T5

1

T6

1