Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T14,T24
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T24
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T24
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T24,T51
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T24
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13684154	14328	0	0
gen_assertions[0].RstEnOn_A	13684154	1106	0	0
gen_assertions[0].RstNOff_A	13684154	14328	0	0
gen_assertions[0].RstNOn_A	13684154	1106	0	0
gen_assertions[1].RstEnOff_A	54735181	12971	0	0
gen_assertions[1].RstEnOn_A	54735181	1066	0	0
gen_assertions[1].RstNOff_A	54735181	12971	0	0
gen_assertions[1].RstNOn_A	54735181	1066	0	0
gen_assertions[2].RstEnOff_A	27368445	13038	0	0
gen_assertions[2].RstEnOn_A	27368445	1069	0	0
gen_assertions[2].RstNOff_A	27368445	13038	0	0
gen_assertions[2].RstNOn_A	27368445	1069	0	0
gen_assertions[3].RstEnOff_A	27368588	13078	0	0
gen_assertions[3].RstEnOn_A	27368588	1115	0	0
gen_assertions[3].RstNOff_A	27368588	13078	0	0
gen_assertions[3].RstNOn_A	27368588	1115	0	0
gen_assertions[4].RstEnOff_A	1728487	22889	0	0
gen_assertions[4].RstEnOn_A	1728487	1169	0	0
gen_assertions[4].RstNOff_A	1728487	22889	0	0
gen_assertions[4].RstNOn_A	1728487	1169	0	0
gen_assertions[5].RstEnOff_A	13684154	14577	0	0
gen_assertions[5].RstEnOn_A	13684154	1227	0	0
gen_assertions[5].RstNOff_A	13684154	14577	0	0
gen_assertions[5].RstNOn_A	13684154	1227	0	0
gen_assertions[6].RstEnOff_A	13684154	14637	0	0
gen_assertions[6].RstEnOn_A	13684154	1288	0	0
gen_assertions[6].RstNOff_A	13684154	14637	0	0
gen_assertions[6].RstNOn_A	13684154	1288	0	0
gen_assertions[7].RstEnOff_A	13684154	14682	0	0
gen_assertions[7].RstEnOn_A	13684154	1329	0	0
gen_assertions[7].RstNOff_A	13684154	14682	0	0
gen_assertions[7].RstNOn_A	13684154	1329	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	14328	0	0
T4	91965	173	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	5	0	0
T10	50549	88	0	0
T11	2385	4	0	0
T12	3487	0	0	0
T13	4414	4	0	0
T14	0	16	0	0
T21	0	12	0	0
T22	0	75	0	0
T23	0	4	0	0
T24	0	226	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	1106	0	0
T4	91965	25	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	1	0	0
T10	50549	1	0	0
T11	2385	0	0	0
T12	3487	0	0	0
T13	4414	0	0	0
T14	0	4	0	0
T24	0	20	0	0
T51	0	39	0	0
T53	0	4	0	0
T54	0	2	0	0
T55	0	26	0	0
T56	0	37	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	14328	0	0
T4	91965	173	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	5	0	0
T10	50549	88	0	0
T11	2385	4	0	0
T12	3487	0	0	0
T13	4414	4	0	0
T14	0	16	0	0
T21	0	12	0	0
T22	0	75	0	0
T23	0	4	0	0
T24	0	226	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	1106	0	0
T4	91965	25	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	1	0	0
T10	50549	1	0	0
T11	2385	0	0	0
T12	3487	0	0	0
T13	4414	0	0	0
T14	0	4	0	0
T24	0	20	0	0
T51	0	39	0	0
T53	0	4	0	0
T54	0	2	0	0
T55	0	26	0	0
T56	0	37	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54735181	12971	0	0
T4	367789	146	0	0
T5	7492	0	0	0
T6	7255	0	0	0
T7	16017	0	0	0
T8	23366	0	0	0
T9	11911	4	0	0
T10	202167	80	0	0
T11	9543	3	0	0
T12	13951	0	0	0
T13	17663	3	0	0
T14	0	14	0	0
T21	0	9	0	0
T22	0	69	0	0
T23	0	4	0	0
T24	0	203	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54735181	1066	0	0
T4	367789	19	0	0
T5	7492	0	0	0
T6	7255	0	0	0
T7	16017	0	0	0
T8	23366	0	0	0
T9	11911	0	0	0
T10	202167	0	0	0
T11	9543	0	0	0
T12	13951	0	0	0
T13	17663	0	0	0
T14	0	1	0	0
T24	0	14	0	0
T36	0	24	0	0
T38	0	1	0	0
T51	0	41	0	0
T53	0	6	0	0
T54	0	1	0	0
T55	0	23	0	0
T56	0	30	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54735181	12971	0	0
T4	367789	146	0	0
T5	7492	0	0	0
T6	7255	0	0	0
T7	16017	0	0	0
T8	23366	0	0	0
T9	11911	4	0	0
T10	202167	80	0	0
T11	9543	3	0	0
T12	13951	0	0	0
T13	17663	3	0	0
T14	0	14	0	0
T21	0	9	0	0
T22	0	69	0	0
T23	0	4	0	0
T24	0	203	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54735181	1066	0	0
T4	367789	19	0	0
T5	7492	0	0	0
T6	7255	0	0	0
T7	16017	0	0	0
T8	23366	0	0	0
T9	11911	0	0	0
T10	202167	0	0	0
T11	9543	0	0	0
T12	13951	0	0	0
T13	17663	0	0	0
T14	0	1	0	0
T24	0	14	0	0
T36	0	24	0	0
T38	0	1	0	0
T51	0	41	0	0
T53	0	6	0	0
T54	0	1	0	0
T55	0	23	0	0
T56	0	30	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27368445	13038	0	0
T4	183906	149	0	0
T5	3745	0	0	0
T6	3628	0	0	0
T7	8008	0	0	0
T8	11680	0	0	0
T9	5952	4	0	0
T10	101088	81	0	0
T11	4771	3	0	0
T12	6974	0	0	0
T13	8830	3	0	0
T14	0	14	0	0
T21	0	9	0	0
T22	0	69	0	0
T23	0	4	0	0
T24	0	206	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27368445	1069	0	0
T4	183906	21	0	0
T5	3745	0	0	0
T6	3628	0	0	0
T7	8008	0	0	0
T8	11680	0	0	0
T9	5952	0	0	0
T10	101088	1	0	0
T11	4771	0	0	0
T12	6974	0	0	0
T13	8830	0	0	0
T24	0	15	0	0
T36	0	22	0	0
T38	0	1	0	0
T39	0	6	0	0
T51	0	38	0	0
T53	0	6	0	0
T55	0	24	0	0
T56	0	34	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27368445	13038	0	0
T4	183906	149	0	0
T5	3745	0	0	0
T6	3628	0	0	0
T7	8008	0	0	0
T8	11680	0	0	0
T9	5952	4	0	0
T10	101088	81	0	0
T11	4771	3	0	0
T12	6974	0	0	0
T13	8830	3	0	0
T14	0	14	0	0
T21	0	9	0	0
T22	0	69	0	0
T23	0	4	0	0
T24	0	206	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27368445	1069	0	0
T4	183906	21	0	0
T5	3745	0	0	0
T6	3628	0	0	0
T7	8008	0	0	0
T8	11680	0	0	0
T9	5952	0	0	0
T10	101088	1	0	0
T11	4771	0	0	0
T12	6974	0	0	0
T13	8830	0	0	0
T24	0	15	0	0
T36	0	22	0	0
T38	0	1	0	0
T39	0	6	0	0
T51	0	38	0	0
T53	0	6	0	0
T55	0	24	0	0
T56	0	34	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27368588	13078	0	0
T4	183904	150	0	0
T5	3745	0	0	0
T6	3628	0	0	0
T7	8008	0	0	0
T8	11685	0	0	0
T9	5953	5	0	0
T10	101089	81	0	0
T11	4771	3	0	0
T12	6975	0	0	0
T13	8835	3	0	0
T14	0	14	0	0
T21	0	9	0	0
T22	0	69	0	0
T23	0	4	0	0
T24	0	210	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27368588	1115	0	0
T4	183904	22	0	0
T5	3745	0	0	0
T6	3628	0	0	0
T7	8008	0	0	0
T8	11685	0	0	0
T9	5953	1	0	0
T10	101089	1	0	0
T11	4771	0	0	0
T12	6975	0	0	0
T13	8835	0	0	0
T24	0	21	0	0
T36	0	23	0	0
T39	0	6	0	0
T51	0	37	0	0
T53	0	6	0	0
T55	0	27	0	0
T56	0	23	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27368588	13078	0	0
T4	183904	150	0	0
T5	3745	0	0	0
T6	3628	0	0	0
T7	8008	0	0	0
T8	11685	0	0	0
T9	5953	5	0	0
T10	101089	81	0	0
T11	4771	3	0	0
T12	6975	0	0	0
T13	8835	3	0	0
T14	0	14	0	0
T21	0	9	0	0
T22	0	69	0	0
T23	0	4	0	0
T24	0	210	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27368588	1115	0	0
T4	183904	22	0	0
T5	3745	0	0	0
T6	3628	0	0	0
T7	8008	0	0	0
T8	11685	0	0	0
T9	5953	1	0	0
T10	101089	1	0	0
T11	4771	0	0	0
T12	6975	0	0	0
T13	8835	0	0	0
T24	0	21	0	0
T36	0	23	0	0
T39	0	6	0	0
T51	0	37	0	0
T53	0	6	0	0
T55	0	27	0	0
T56	0	23	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1728487	22889	0	0
T1	731	3	0	0
T2	653	2	0	0
T3	252	2	0	0
T4	11748	237	0	0
T5	233	1	0	0
T6	225	1	0	0
T7	500	2	0	0
T8	731	3	0	0
T9	371	6	0	0
T10	6409	127	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1728487	1169	0	0
T4	11748	23	0	0
T5	233	0	0	0
T6	225	0	0	0
T7	500	0	0	0
T8	731	0	0	0
T9	371	0	0	0
T10	6409	1	0	0
T11	298	0	0	0
T12	434	0	0	0
T13	551	0	0	0
T24	0	19	0	0
T36	0	28	0	0
T39	0	7	0	0
T43	0	6	0	0
T51	0	37	0	0
T53	0	8	0	0
T55	0	22	0	0
T56	0	36	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1728487	22889	0	0
T1	731	3	0	0
T2	653	2	0	0
T3	252	2	0	0
T4	11748	237	0	0
T5	233	1	0	0
T6	225	1	0	0
T7	500	2	0	0
T8	731	3	0	0
T9	371	6	0	0
T10	6409	127	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1728487	1169	0	0
T4	11748	23	0	0
T5	233	0	0	0
T6	225	0	0	0
T7	500	0	0	0
T8	731	0	0	0
T9	371	0	0	0
T10	6409	1	0	0
T11	298	0	0	0
T12	434	0	0	0
T13	551	0	0	0
T24	0	19	0	0
T36	0	28	0	0
T39	0	7	0	0
T43	0	6	0	0
T51	0	37	0	0
T53	0	8	0	0
T55	0	22	0	0
T56	0	36	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	14577	0	0
T4	91965	166	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	4	0	0
T10	50549	87	0	0
T11	2385	4	0	0
T12	3487	0	0	0
T13	4414	4	0	0
T14	0	16	0	0
T21	0	12	0	0
T22	0	75	0	0
T23	0	4	0	0
T24	0	222	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	1227	0	0
T4	91965	18	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	0	0	0
T10	50549	0	0	0
T11	2385	0	0	0
T12	3487	0	0	0
T13	4414	0	0	0
T24	0	16	0	0
T36	0	25	0	0
T38	0	1	0	0
T39	0	9	0	0
T43	0	5	0	0
T51	0	36	0	0
T53	0	10	0	0
T55	0	26	0	0
T56	0	33	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	14577	0	0
T4	91965	166	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	4	0	0
T10	50549	87	0	0
T11	2385	4	0	0
T12	3487	0	0	0
T13	4414	4	0	0
T14	0	16	0	0
T21	0	12	0	0
T22	0	75	0	0
T23	0	4	0	0
T24	0	222	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	1227	0	0
T4	91965	18	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	0	0	0
T10	50549	0	0	0
T11	2385	0	0	0
T12	3487	0	0	0
T13	4414	0	0	0
T24	0	16	0	0
T36	0	25	0	0
T38	0	1	0	0
T39	0	9	0	0
T43	0	5	0	0
T51	0	36	0	0
T53	0	10	0	0
T55	0	26	0	0
T56	0	33	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	14637	0	0
T4	91965	165	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	5	0	0
T10	50549	88	0	0
T11	2385	4	0	0
T12	3487	0	0	0
T13	4414	4	0	0
T14	0	16	0	0
T21	0	12	0	0
T22	0	75	0	0
T23	0	5	0	0
T24	0	225	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	1288	0	0
T4	91965	18	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	1	0	0
T10	50549	1	0	0
T11	2385	0	0	0
T12	3487	0	0	0
T13	4414	0	0	0
T23	0	1	0	0
T24	0	21	0	0
T36	0	24	0	0
T51	0	39	0	0
T53	0	12	0	0
T55	0	27	0	0
T56	0	35	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	14637	0	0
T4	91965	165	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	5	0	0
T10	50549	88	0	0
T11	2385	4	0	0
T12	3487	0	0	0
T13	4414	4	0	0
T14	0	16	0	0
T21	0	12	0	0
T22	0	75	0	0
T23	0	5	0	0
T24	0	225	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	1288	0	0
T4	91965	18	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	1	0	0
T10	50549	1	0	0
T11	2385	0	0	0
T12	3487	0	0	0
T13	4414	0	0	0
T23	0	1	0	0
T24	0	21	0	0
T36	0	24	0	0
T51	0	39	0	0
T53	0	12	0	0
T55	0	27	0	0
T56	0	35	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	14682	0	0
T4	91965	169	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	4	0	0
T10	50549	88	0	0
T11	2385	4	0	0
T12	3487	0	0	0
T13	4414	4	0	0
T14	0	16	0	0
T21	0	12	0	0
T22	0	75	0	0
T23	0	4	0	0
T24	0	225	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	1329	0	0
T4	91965	21	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	0	0	0
T10	50549	1	0	0
T11	2385	0	0	0
T12	3487	0	0	0
T13	4414	0	0	0
T24	0	20	0	0
T36	0	25	0	0
T39	0	10	0	0
T43	0	9	0	0
T51	0	43	0	0
T53	0	12	0	0
T55	0	29	0	0
T56	0	35	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	14682	0	0
T4	91965	169	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	4	0	0
T10	50549	88	0	0
T11	2385	4	0	0
T12	3487	0	0	0
T13	4414	4	0	0
T14	0	16	0	0
T21	0	12	0	0
T22	0	75	0	0
T23	0	4	0	0
T24	0	225	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	1329	0	0
T4	91965	21	0	0
T5	1871	0	0	0
T6	1813	0	0	0
T7	4003	0	0	0
T8	5839	0	0	0
T9	2976	0	0	0
T10	50549	1	0	0
T11	2385	0	0	0
T12	3487	0	0	0
T13	4414	0	0	0
T24	0	20	0	0
T36	0	25	0	0
T39	0	10	0	0
T43	0	9	0	0
T51	0	43	0	0
T53	0	12	0	0
T55	0	29	0	0
T56	0	35	0	0