Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12907573	7791	0	0
alert_regwen_rd_A	12907573	5372	0	0
cpu_regwen_rd_A	12907573	5400	0	0
sw_rst_ctrl_n_0_rd_A	12907573	9655	0	0
sw_rst_ctrl_n_1_rd_A	12907573	9731	0	0
sw_rst_ctrl_n_2_rd_A	12907573	9932	0	0
sw_rst_ctrl_n_3_rd_A	12907573	9867	0	0
sw_rst_ctrl_n_4_rd_A	12907573	9908	0	0
sw_rst_ctrl_n_5_rd_A	12907573	9646	0	0
sw_rst_ctrl_n_6_rd_A	12907573	9974	0	0
sw_rst_ctrl_n_7_rd_A	12907573	10012	0	0
sw_rst_regwen_0_rd_A	12907573	5774	0	0
sw_rst_regwen_1_rd_A	12907573	6007	0	0
sw_rst_regwen_2_rd_A	12907573	5711	0	0
sw_rst_regwen_3_rd_A	12907573	6104	0	0
sw_rst_regwen_4_rd_A	12907573	5913	0	0
sw_rst_regwen_5_rd_A	12907573	5779	0	0
sw_rst_regwen_6_rd_A	12907573	5845	0	0
sw_rst_regwen_7_rd_A	12907573	6058	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	7791	0	0
T65	10069	407	0	0
T66	3134	184	0	0
T67	2379	6	0	0
T68	16516	5	0	0
T69	19764	1	0	0
T84	3595	60	0	0
T85	4496	777	0	0
T86	4667	648	0	0
T90	4420	148	0	0
T93	4709	20	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	5372	0	0
T15	5527	0	0	0
T26	41729	0	0	0
T36	132730	0	0	0
T37	5087	0	0	0
T38	2741	0	0	0
T39	7367	0	0	0
T40	4571	0	0	0
T41	1610	0	0	0
T55	181346	206	0	0
T56	62159	0	0	0
T96	0	103	0	0
T98	0	49	0	0
T100	0	345	0	0
T103	0	62	0	0
T113	0	160	0	0
T114	0	93	0	0
T115	0	551	0	0
T116	0	121	0	0
T117	0	48	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	5400	0	0
T15	5527	0	0	0
T26	41729	0	0	0
T36	132730	0	0	0
T37	5087	0	0	0
T38	2741	0	0	0
T39	7367	0	0	0
T40	4571	0	0	0
T41	1610	0	0	0
T55	181346	267	0	0
T56	62159	0	0	0
T96	0	80	0	0
T98	0	43	0	0
T100	0	319	0	0
T103	0	70	0	0
T113	0	209	0	0
T114	0	61	0	0
T115	0	519	0	0
T116	0	97	0	0
T117	0	41	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	9655	0	0
T15	5527	0	0	0
T23	5483	16	0	0
T24	162689	0	0	0
T26	41729	0	0	0
T43	0	124	0	0
T51	46230	0	0	0
T52	1649	0	0	0
T53	7934	0	0	0
T54	4453	0	0	0
T55	181346	568	0	0
T56	62159	0	0	0
T96	0	92	0	0
T98	0	35	0	0
T100	0	440	0	0
T118	0	12	0	0
T119	0	68	0	0
T120	0	8	0	0
T121	0	12	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	9731	0	0
T15	5527	0	0	0
T23	5483	6	0	0
T24	162689	0	0	0
T26	41729	0	0	0
T43	0	122	0	0
T51	46230	0	0	0
T52	1649	0	0	0
T53	7934	0	0	0
T54	4453	0	0	0
T55	181346	542	0	0
T56	62159	0	0	0
T96	0	87	0	0
T98	0	59	0	0
T100	0	443	0	0
T118	0	9	0	0
T119	0	43	0	0
T120	0	21	0	0
T121	0	19	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	9932	0	0
T15	5527	0	0	0
T23	5483	6	0	0
T24	162689	0	0	0
T26	41729	0	0	0
T43	0	142	0	0
T51	46230	0	0	0
T52	1649	0	0	0
T53	7934	0	0	0
T54	4453	0	0	0
T55	181346	599	0	0
T56	62159	0	0	0
T96	0	100	0	0
T98	0	48	0	0
T100	0	425	0	0
T118	0	21	0	0
T119	0	74	0	0
T120	0	11	0	0
T121	0	12	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	9867	0	0
T15	5527	0	0	0
T23	5483	4	0	0
T24	162689	0	0	0
T26	41729	0	0	0
T43	0	132	0	0
T51	46230	0	0	0
T52	1649	0	0	0
T53	7934	0	0	0
T54	4453	0	0	0
T55	181346	529	0	0
T56	62159	0	0	0
T96	0	92	0	0
T98	0	51	0	0
T100	0	477	0	0
T118	0	11	0	0
T119	0	67	0	0
T120	0	9	0	0
T121	0	19	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	9908	0	0
T15	5527	0	0	0
T23	5483	5	0	0
T24	162689	0	0	0
T26	41729	0	0	0
T43	0	117	0	0
T51	46230	0	0	0
T52	1649	0	0	0
T53	7934	0	0	0
T54	4453	0	0	0
T55	181346	558	0	0
T56	62159	0	0	0
T96	0	96	0	0
T98	0	36	0	0
T100	0	522	0	0
T118	0	17	0	0
T119	0	44	0	0
T120	0	20	0	0
T121	0	13	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	9646	0	0
T15	5527	0	0	0
T23	5483	4	0	0
T24	162689	0	0	0
T26	41729	0	0	0
T43	0	106	0	0
T51	46230	0	0	0
T52	1649	0	0	0
T53	7934	0	0	0
T54	4453	0	0	0
T55	181346	593	0	0
T56	62159	0	0	0
T96	0	81	0	0
T98	0	64	0	0
T100	0	394	0	0
T118	0	14	0	0
T119	0	59	0	0
T120	0	18	0	0
T121	0	14	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	9974	0	0
T15	5527	0	0	0
T23	5483	17	0	0
T24	162689	0	0	0
T26	41729	0	0	0
T43	0	102	0	0
T51	46230	0	0	0
T52	1649	0	0	0
T53	7934	0	0	0
T54	4453	0	0	0
T55	181346	586	0	0
T56	62159	0	0	0
T96	0	87	0	0
T98	0	56	0	0
T100	0	469	0	0
T118	0	6	0	0
T119	0	64	0	0
T120	0	26	0	0
T121	0	10	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	10012	0	0
T15	5527	0	0	0
T23	5483	16	0	0
T24	162689	0	0	0
T26	41729	0	0	0
T43	0	114	0	0
T51	46230	0	0	0
T52	1649	0	0	0
T53	7934	0	0	0
T54	4453	0	0	0
T55	181346	529	0	0
T56	62159	0	0	0
T96	0	76	0	0
T98	0	50	0	0
T100	0	439	0	0
T118	0	10	0	0
T119	0	80	0	0
T120	0	20	0	0
T121	0	20	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	5774	0	0
T15	5527	0	0	0
T26	41729	0	0	0
T36	132730	0	0	0
T37	5087	0	0	0
T38	2741	0	0	0
T39	7367	0	0	0
T40	4571	0	0	0
T41	1610	0	0	0
T43	0	37	0	0
T55	181346	198	0	0
T56	62159	0	0	0
T96	0	68	0	0
T98	0	62	0	0
T100	0	314	0	0
T118	0	1	0	0
T119	0	14	0	0
T120	0	2	0	0
T121	0	6	0	0
T122	0	7	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	6007	0	0
T15	5527	0	0	0
T23	5483	7	0	0
T24	162689	0	0	0
T26	41729	0	0	0
T43	0	28	0	0
T51	46230	0	0	0
T52	1649	0	0	0
T53	7934	0	0	0
T54	4453	0	0	0
T55	181346	227	0	0
T56	62159	0	0	0
T96	0	97	0	0
T98	0	48	0	0
T100	0	340	0	0
T118	0	6	0	0
T119	0	18	0	0
T120	0	12	0	0
T121	0	7	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	5711	0	0
T15	5527	0	0	0
T26	41729	0	0	0
T36	132730	0	0	0
T37	5087	0	0	0
T38	2741	0	0	0
T39	7367	0	0	0
T40	4571	0	0	0
T41	1610	0	0	0
T43	0	31	0	0
T55	181346	212	0	0
T56	62159	0	0	0
T96	0	89	0	0
T98	0	66	0	0
T100	0	320	0	0
T118	0	1	0	0
T119	0	24	0	0
T120	0	4	0	0
T121	0	10	0	0
T122	0	4	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	6104	0	0
T15	5527	0	0	0
T26	41729	0	0	0
T36	132730	0	0	0
T37	5087	0	0	0
T38	2741	0	0	0
T39	7367	0	0	0
T40	4571	0	0	0
T41	1610	0	0	0
T43	0	34	0	0
T55	181346	212	0	0
T56	62159	0	0	0
T96	0	64	0	0
T98	0	59	0	0
T100	0	389	0	0
T118	0	7	0	0
T119	0	7	0	0
T120	0	14	0	0
T121	0	1	0	0
T122	0	9	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	5913	0	0
T15	5527	0	0	0
T23	5483	8	0	0
T24	162689	0	0	0
T26	41729	0	0	0
T43	0	46	0	0
T51	46230	0	0	0
T52	1649	0	0	0
T53	7934	0	0	0
T54	4453	0	0	0
T55	181346	266	0	0
T56	62159	0	0	0
T96	0	105	0	0
T98	0	34	0	0
T100	0	309	0	0
T118	0	7	0	0
T119	0	31	0	0
T120	0	15	0	0
T122	0	11	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	5779	0	0
T15	5527	0	0	0
T23	5483	5	0	0
T24	162689	0	0	0
T26	41729	0	0	0
T43	0	35	0	0
T51	46230	0	0	0
T52	1649	0	0	0
T53	7934	0	0	0
T54	4453	0	0	0
T55	181346	212	0	0
T56	62159	0	0	0
T96	0	92	0	0
T98	0	48	0	0
T100	0	313	0	0
T118	0	5	0	0
T119	0	11	0	0
T120	0	7	0	0
T121	0	4	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	5845	0	0
T15	5527	0	0	0
T26	41729	0	0	0
T36	132730	0	0	0
T37	5087	0	0	0
T38	2741	0	0	0
T39	7367	0	0	0
T40	4571	0	0	0
T41	1610	0	0	0
T43	0	45	0	0
T55	181346	222	0	0
T56	62159	0	0	0
T96	0	111	0	0
T98	0	81	0	0
T100	0	360	0	0
T118	0	10	0	0
T119	0	9	0	0
T120	0	2	0	0
T121	0	5	0	0
T122	0	12	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12907573	6058	0	0
T15	5527	0	0	0
T23	5483	18	0	0
T24	162689	0	0	0
T26	41729	0	0	0
T43	0	35	0	0
T51	46230	0	0	0
T52	1649	0	0	0
T53	7934	0	0	0
T54	4453	0	0	0
T55	181346	232	0	0
T56	62159	0	0	0
T96	0	91	0	0
T98	0	57	0	0
T100	0	282	0	0
T119	0	21	0	0
T120	0	4	0	0
T121	0	5	0	0
T122	0	7	0	0