Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	12149490	13401	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	12149490	123639	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	12149490	6861953	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	12149490	197510	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	12149490	13401	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	12149490	123639	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	12149490	6861953	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	12149490	197510	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	13401	0	0
T4	73010	148	0	0
T5	1829	0	0	0
T6	1794	0	0	0
T7	3889	0	0	0
T8	5487	0	0	0
T9	2734	4	0	0
T10	39558	87	0	0
T11	2144	4	0	0
T12	3373	0	0	0
T13	4033	4	0	0
T14	0	16	0	0
T21	0	12	0	0
T22	0	75	0	0
T23	0	4	0	0
T24	0	207	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	123639	0	0
T4	73010	1350	0	0
T5	1829	0	0	0
T6	1794	0	0	0
T7	3889	0	0	0
T8	5487	0	0	0
T9	2734	37	0	0
T10	39558	800	0	0
T11	2144	38	0	0
T12	3373	0	0	0
T13	4033	38	0	0
T14	0	144	0	0
T21	0	108	0	0
T22	0	701	0	0
T23	0	38	0	0
T24	0	1920	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	6861953	0	0
T1	5675	578	0	0
T2	5100	633	0	0
T3	1913	932	0	0
T4	73010	39766	0	0
T5	1829	1211	0	0
T6	1794	1149	0	0
T7	3889	932	0	0
T8	5487	576	0	0
T9	2734	1794	0	0
T10	39558	20400	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	197510	0	0
T4	73010	2192	0	0
T5	1829	0	0	0
T6	1794	0	0	0
T7	3889	0	0	0
T8	5487	0	0	0
T9	2734	72	0	0
T10	39558	1321	0	0
T11	2144	51	0	0
T12	3373	0	0	0
T13	4033	54	0	0
T14	0	223	0	0
T21	0	173	0	0
T22	0	1130	0	0
T23	0	57	0	0
T24	0	3041	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	13401	0	0
T4	73010	148	0	0
T5	1829	0	0	0
T6	1794	0	0	0
T7	3889	0	0	0
T8	5487	0	0	0
T9	2734	4	0	0
T10	39558	87	0	0
T11	2144	4	0	0
T12	3373	0	0	0
T13	4033	4	0	0
T14	0	16	0	0
T21	0	12	0	0
T22	0	75	0	0
T23	0	4	0	0
T24	0	207	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	123639	0	0
T4	73010	1350	0	0
T5	1829	0	0	0
T6	1794	0	0	0
T7	3889	0	0	0
T8	5487	0	0	0
T9	2734	37	0	0
T10	39558	800	0	0
T11	2144	38	0	0
T12	3373	0	0	0
T13	4033	38	0	0
T14	0	144	0	0
T21	0	108	0	0
T22	0	701	0	0
T23	0	38	0	0
T24	0	1920	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	6861953	0	0
T1	5675	578	0	0
T2	5100	633	0	0
T3	1913	932	0	0
T4	73010	39766	0	0
T5	1829	1211	0	0
T6	1794	1149	0	0
T7	3889	932	0	0
T8	5487	576	0	0
T9	2734	1794	0	0
T10	39558	20400	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	197510	0	0
T4	73010	2192	0	0
T5	1829	0	0	0
T6	1794	0	0	0
T7	3889	0	0	0
T8	5487	0	0	0
T9	2734	72	0	0
T10	39558	1321	0	0
T11	2144	51	0	0
T12	3373	0	0	0
T13	4033	54	0	0
T14	0	223	0	0
T21	0	173	0	0
T22	0	1130	0	0
T23	0	57	0	0
T24	0	3041	0	0