Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T10
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T10,T24

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T9,T10
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	57017649	9688	0	0
CascadeEffAonToRstPorAboveRise_A	57017649	9688	0	0
CascadeEffAonToRstPorIoAboveFall_A	54735181	9688	0	0
CascadeEffAonToRstPorIoAboveRise_A	54735181	9688	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27368445	9688	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27368445	9688	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13684154	9688	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13684154	9688	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27368588	9688	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27368588	9688	0	0
CascadeLcToLcAboveFall_A	57017649	23089	0	0
CascadeLcToLcAboveRise_A	57017649	23089	0	0
CascadeLcToLcAonAboveFall_A	1728487	23089	0	0
CascadeLcToLcAonAboveRise_A	1728487	23089	0	0
CascadeLcToLcShadowedAboveFall_A	57017649	23089	0	0
CascadeLcToLcShadowedAboveRise_A	57017649	23089	0	0
CascadePorToAonAboveFall_A	1728487	7762	0	0
CascadeSysToSysAboveFall_A	57017649	23089	0	0
CascadeSysToSysAboveRise_A	57017649	23089	0	0
ScanRstToAonRise_A	1728487	245	0	0
StablePorToAonRise_A	1728487	9688	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12149490	23089	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12149490	23089	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12149490	23089	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12149490	23089	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13684154	23089	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13684154	23089	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12149490	23089	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12149490	23089	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12149490	23089	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12149490	23089	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57017649	9688	0	0
T1	24332	8	0	0
T2	21830	2	0	0
T3	8452	2	0	0
T4	383128	75	0	0
T5	7805	1	0	0
T6	7558	1	0	0
T7	16685	2	0	0
T8	24321	8	0	0
T9	12402	2	0	0
T10	210611	43	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57017649	9688	0	0
T1	24332	8	0	0
T2	21830	2	0	0
T3	8452	2	0	0
T4	383128	75	0	0
T5	7805	1	0	0
T6	7558	1	0	0
T7	16685	2	0	0
T8	24321	8	0	0
T9	12402	2	0	0
T10	210611	43	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54735181	9688	0	0
T1	23350	8	0	0
T2	20957	2	0	0
T3	8113	2	0	0
T4	367789	75	0	0
T5	7492	1	0	0
T6	7255	1	0	0
T7	16017	2	0	0
T8	23366	8	0	0
T9	11911	2	0	0
T10	202167	43	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54735181	9688	0	0
T1	23350	8	0	0
T2	20957	2	0	0
T3	8113	2	0	0
T4	367789	75	0	0
T5	7492	1	0	0
T6	7255	1	0	0
T7	16017	2	0	0
T8	23366	8	0	0
T9	11911	2	0	0
T10	202167	43	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27368445	9688	0	0
T1	11673	8	0	0
T2	10478	2	0	0
T3	4056	2	0	0
T4	183906	75	0	0
T5	3745	1	0	0
T6	3628	1	0	0
T7	8008	2	0	0
T8	11680	8	0	0
T9	5952	2	0	0
T10	101088	43	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27368445	9688	0	0
T1	11673	8	0	0
T2	10478	2	0	0
T3	4056	2	0	0
T4	183906	75	0	0
T5	3745	1	0	0
T6	3628	1	0	0
T7	8008	2	0	0
T8	11680	8	0	0
T9	5952	2	0	0
T10	101088	43	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	9688	0	0
T1	5837	8	0	0
T2	5239	2	0	0
T3	2027	2	0	0
T4	91965	75	0	0
T5	1871	1	0	0
T6	1813	1	0	0
T7	4003	2	0	0
T8	5839	8	0	0
T9	2976	2	0	0
T10	50549	43	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	9688	0	0
T1	5837	8	0	0
T2	5239	2	0	0
T3	2027	2	0	0
T4	91965	75	0	0
T5	1871	1	0	0
T6	1813	1	0	0
T7	4003	2	0	0
T8	5839	8	0	0
T9	2976	2	0	0
T10	50549	43	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27368588	9688	0	0
T1	11671	8	0	0
T2	10479	2	0	0
T3	4056	2	0	0
T4	183904	75	0	0
T5	3745	1	0	0
T6	3628	1	0	0
T7	8008	2	0	0
T8	11685	8	0	0
T9	5953	2	0	0
T10	101089	43	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27368588	9688	0	0
T1	11671	8	0	0
T2	10479	2	0	0
T3	4056	2	0	0
T4	183904	75	0	0
T5	3745	1	0	0
T6	3628	1	0	0
T7	8008	2	0	0
T8	11685	8	0	0
T9	5953	2	0	0
T10	101089	43	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57017649	23089	0	0
T1	24332	8	0	0
T2	21830	2	0	0
T3	8452	2	0	0
T4	383128	223	0	0
T5	7805	1	0	0
T6	7558	1	0	0
T7	16685	2	0	0
T8	24321	8	0	0
T9	12402	6	0	0
T10	210611	130	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57017649	23089	0	0
T1	24332	8	0	0
T2	21830	2	0	0
T3	8452	2	0	0
T4	383128	223	0	0
T5	7805	1	0	0
T6	7558	1	0	0
T7	16685	2	0	0
T8	24321	8	0	0
T9	12402	6	0	0
T10	210611	130	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1728487	23089	0	0
T1	731	8	0	0
T2	653	2	0	0
T3	252	2	0	0
T4	11748	223	0	0
T5	233	1	0	0
T6	225	1	0	0
T7	500	2	0	0
T8	731	8	0	0
T9	371	6	0	0
T10	6409	130	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1728487	23089	0	0
T1	731	8	0	0
T2	653	2	0	0
T3	252	2	0	0
T4	11748	223	0	0
T5	233	1	0	0
T6	225	1	0	0
T7	500	2	0	0
T8	731	8	0	0
T9	371	6	0	0
T10	6409	130	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57017649	23089	0	0
T1	24332	8	0	0
T2	21830	2	0	0
T3	8452	2	0	0
T4	383128	223	0	0
T5	7805	1	0	0
T6	7558	1	0	0
T7	16685	2	0	0
T8	24321	8	0	0
T9	12402	6	0	0
T10	210611	130	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57017649	23089	0	0
T1	24332	8	0	0
T2	21830	2	0	0
T3	8452	2	0	0
T4	383128	223	0	0
T5	7805	1	0	0
T6	7558	1	0	0
T7	16685	2	0	0
T8	24321	8	0	0
T9	12402	6	0	0
T10	210611	130	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1728487	7762	0	0
T1	731	8	0	0
T2	653	20	0	0
T3	252	2	0	0
T4	11748	34	0	0
T5	233	1	0	0
T6	225	1	0	0
T7	500	13	0	0
T8	731	8	0	0
T9	371	1	0	0
T10	6409	18	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57017649	23089	0	0
T1	24332	8	0	0
T2	21830	2	0	0
T3	8452	2	0	0
T4	383128	223	0	0
T5	7805	1	0	0
T6	7558	1	0	0
T7	16685	2	0	0
T8	24321	8	0	0
T9	12402	6	0	0
T10	210611	130	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57017649	23089	0	0
T1	24332	8	0	0
T2	21830	2	0	0
T3	8452	2	0	0
T4	383128	223	0	0
T5	7805	1	0	0
T6	7558	1	0	0
T7	16685	2	0	0
T8	24321	8	0	0
T9	12402	6	0	0
T10	210611	130	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1728487	245	0	0
T4	11748	6	0	0
T5	233	0	0	0
T6	225	0	0	0
T7	500	0	0	0
T8	731	0	0	0
T9	371	0	0	0
T10	6409	2	0	0
T11	298	0	0	0
T12	434	0	0	0
T13	551	0	0	0
T24	0	6	0	0
T36	0	5	0	0
T51	0	2	0	0
T55	0	3	0	0
T56	0	3	0	0
T97	0	3	0	0
T99	0	3	0	0
T121	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1728487	9688	0	0
T1	731	8	0	0
T2	653	2	0	0
T3	252	2	0	0
T4	11748	75	0	0
T5	233	1	0	0
T6	225	1	0	0
T7	500	2	0	0
T8	731	8	0	0
T9	371	2	0	0
T10	6409	43	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	23089	0	0
T1	5675	8	0	0
T2	5100	2	0	0
T3	1913	2	0	0
T4	73010	223	0	0
T5	1829	1	0	0
T6	1794	1	0	0
T7	3889	2	0	0
T8	5487	8	0	0
T9	2734	6	0	0
T10	39558	130	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	23089	0	0
T1	5675	8	0	0
T2	5100	2	0	0
T3	1913	2	0	0
T4	73010	223	0	0
T5	1829	1	0	0
T6	1794	1	0	0
T7	3889	2	0	0
T8	5487	8	0	0
T9	2734	6	0	0
T10	39558	130	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	23089	0	0
T1	5675	8	0	0
T2	5100	2	0	0
T3	1913	2	0	0
T4	73010	223	0	0
T5	1829	1	0	0
T6	1794	1	0	0
T7	3889	2	0	0
T8	5487	8	0	0
T9	2734	6	0	0
T10	39558	130	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	23089	0	0
T1	5675	8	0	0
T2	5100	2	0	0
T3	1913	2	0	0
T4	73010	223	0	0
T5	1829	1	0	0
T6	1794	1	0	0
T7	3889	2	0	0
T8	5487	8	0	0
T9	2734	6	0	0
T10	39558	130	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	23089	0	0
T1	5837	8	0	0
T2	5239	2	0	0
T3	2027	2	0	0
T4	91965	223	0	0
T5	1871	1	0	0
T6	1813	1	0	0
T7	4003	2	0	0
T8	5839	8	0	0
T9	2976	6	0	0
T10	50549	130	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13684154	23089	0	0
T1	5837	8	0	0
T2	5239	2	0	0
T3	2027	2	0	0
T4	91965	223	0	0
T5	1871	1	0	0
T6	1813	1	0	0
T7	4003	2	0	0
T8	5839	8	0	0
T9	2976	6	0	0
T10	50549	130	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	23089	0	0
T1	5675	8	0	0
T2	5100	2	0	0
T3	1913	2	0	0
T4	73010	223	0	0
T5	1829	1	0	0
T6	1794	1	0	0
T7	3889	2	0	0
T8	5487	8	0	0
T9	2734	6	0	0
T10	39558	130	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	23089	0	0
T1	5675	8	0	0
T2	5100	2	0	0
T3	1913	2	0	0
T4	73010	223	0	0
T5	1829	1	0	0
T6	1794	1	0	0
T7	3889	2	0	0
T8	5487	8	0	0
T9	2734	6	0	0
T10	39558	130	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	23089	0	0
T1	5675	8	0	0
T2	5100	2	0	0
T3	1913	2	0	0
T4	73010	223	0	0
T5	1829	1	0	0
T6	1794	1	0	0
T7	3889	2	0	0
T8	5487	8	0	0
T9	2734	6	0	0
T10	39558	130	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12149490	23089	0	0
T1	5675	8	0	0
T2	5100	2	0	0
T3	1913	2	0	0
T4	73010	223	0	0
T5	1829	1	0	0
T6	1794	1	0	0
T7	3889	2	0	0
T8	5487	8	0	0
T9	2734	6	0	0
T10	39558	130	0	0