Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	645308	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

388581

1

T1

1104

T3

383

T5

143

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	552357	1			T1	1500		T3	515		T5	186
values[0x0]	240525	1			T1	869		T3	246		T5	97
values[0x1]	241007	1			T1	831		T3	223		T5	96

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	540944	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

492945

1

T1

1418

T3

476

T5

188

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4716	1			T5	5		T9	9		T10	58
valid_sources[0x01]	3233	1			T3	2		T9	4		T10	41
valid_sources[0x02]	3447	1			T3	1		T9	14		T10	36
valid_sources[0x03]	3988	1			T3	4		T5	3		T9	11
valid_sources[0x04]	4085	1			T3	4		T5	2		T9	12
valid_sources[0x05]	4139	1			T3	7		T9	12		T10	49
valid_sources[0x06]	5576	1			T9	7		T10	43		T12	7
valid_sources[0x07]	3052	1			T3	1		T5	1		T9	13
valid_sources[0x08]	3614	1			T3	6		T8	2		T9	8
valid_sources[0x09]	7234	1			T3	2		T9	15		T10	41
valid_sources[0x0a]	4650	1			T3	5		T8	281		T9	13
valid_sources[0x0b]	3892	1			T3	9		T5	1		T8	2
valid_sources[0x0c]	4206	1			T3	3		T8	499		T9	17
valid_sources[0x0d]	3652	1			T3	5		T9	13		T10	41
valid_sources[0x0e]	3078	1			T3	8		T5	2		T9	13
valid_sources[0x0f]	3472	1			T3	5		T5	3		T9	19
valid_sources[0x10]	3667	1			T3	6		T5	1		T9	15
valid_sources[0x11]	3417	1			T3	10		T5	2		T8	3
valid_sources[0x12]	5494	1			T3	4		T9	17		T10	48
valid_sources[0x13]	4268	1			T3	4		T5	1		T9	7
valid_sources[0x14]	3485	1			T3	2		T8	67		T9	6
valid_sources[0x15]	3655	1			T3	5		T5	1		T9	14
valid_sources[0x16]	3158	1			T3	4		T9	12		T10	48
valid_sources[0x17]	4082	1			T3	1		T5	1		T8	13
valid_sources[0x18]	3994	1			T3	4		T9	13		T10	52
valid_sources[0x19]	3646	1			T3	5		T9	9		T10	46
valid_sources[0x1a]	4034	1			T3	4		T5	1		T8	155
valid_sources[0x1b]	3150	1			T3	1		T8	13		T9	18
valid_sources[0x1c]	3466	1			T3	1		T5	3		T8	101
valid_sources[0x1d]	7600	1			T3	2		T9	12		T10	47
valid_sources[0x1e]	3132	1			T3	3		T9	11		T10	37
valid_sources[0x1f]	3745	1			T3	2		T5	6		T9	17
valid_sources[0x20]	4007	1			T3	6		T5	2		T8	65
valid_sources[0x21]	6701	1			T3	2		T9	5		T10	40
valid_sources[0x22]	5136	1			T3	2		T5	5		T6	2
valid_sources[0x23]	3323	1			T3	4		T5	7		T9	18
valid_sources[0x24]	4158	1			T3	3		T5	6		T8	9
valid_sources[0x25]	3850	1			T3	1		T9	8		T10	45
valid_sources[0x26]	3794	1			T3	6		T5	2		T9	14
valid_sources[0x27]	5521	1			T3	3		T5	6		T9	14
valid_sources[0x28]	3332	1			T3	2		T5	2		T8	105
valid_sources[0x29]	3525	1			T3	4		T9	9		T10	44
valid_sources[0x2a]	3864	1			T3	4		T8	111		T9	15
valid_sources[0x2b]	3589	1			T3	2		T5	1		T9	11
valid_sources[0x2c]	3636	1			T3	7		T5	3		T8	6
valid_sources[0x2d]	4304	1			T3	5		T9	8		T10	37
valid_sources[0x2e]	3184	1			T3	2		T9	18		T10	33
valid_sources[0x2f]	3422	1			T3	1		T5	3		T9	11
valid_sources[0x30]	4375	1			T3	3		T9	10		T10	45
valid_sources[0x31]	4363	1			T3	10		T5	2		T6	3
valid_sources[0x32]	3452	1			T3	1		T5	5		T9	10
valid_sources[0x33]	3210	1			T3	5		T9	18		T10	39
valid_sources[0x34]	3750	1			T5	4		T8	153		T9	7
valid_sources[0x35]	3273	1			T3	6		T5	3		T8	70
valid_sources[0x36]	3614	1			T3	4		T8	153		T9	10
valid_sources[0x37]	3722	1			T3	3		T9	19		T10	32
valid_sources[0x38]	6618	1			T3	4		T5	7		T8	5
valid_sources[0x39]	3197	1			T3	1		T8	3		T9	11
valid_sources[0x3a]	4180	1			T3	5		T5	2		T9	22
valid_sources[0x3b]	4409	1			T5	1		T8	70		T9	5
valid_sources[0x3c]	3529	1			T3	5		T8	197		T9	10
valid_sources[0x3d]	4044	1			T3	4		T9	8		T10	51
valid_sources[0x3e]	3428	1			T8	2		T9	16		T10	32
valid_sources[0x3f]	3422	1			T3	3		T5	5		T9	13
valid_sources[0x40]	3462	1			T3	2		T9	9		T10	47
valid_sources[0x41]	3950	1			T3	4		T5	4		T9	19
valid_sources[0x42]	2985	1			T3	4		T9	10		T10	43
valid_sources[0x43]	3330	1			T5	1		T8	70		T9	19
valid_sources[0x44]	3252	1			T3	4		T5	2		T9	13
valid_sources[0x45]	4484	1			T3	6		T5	2		T9	10
valid_sources[0x46]	3467	1			T9	9		T10	44		T11	15
valid_sources[0x47]	4197	1			T3	3		T9	18		T10	48
valid_sources[0x48]	4103	1			T3	3		T5	2		T9	9
valid_sources[0x49]	2979	1			T9	7		T10	36		T12	9
valid_sources[0x4a]	3957	1			T3	1		T8	382		T9	9
valid_sources[0x4b]	4396	1			T3	9		T5	2		T9	14
valid_sources[0x4c]	4006	1			T3	3		T9	20		T10	41
valid_sources[0x4d]	3254	1			T3	5		T5	2		T8	13
valid_sources[0x4e]	4415	1			T3	3		T5	2		T9	11
valid_sources[0x4f]	3770	1			T3	9		T9	11		T10	36
valid_sources[0x50]	3581	1			T3	6		T5	1		T9	8
valid_sources[0x51]	3188	1			T3	3		T5	1		T9	11
valid_sources[0x52]	3387	1			T3	6		T9	14		T10	40
valid_sources[0x53]	3861	1			T3	4		T5	2		T9	12
valid_sources[0x54]	3550	1			T3	2		T5	4		T9	19
valid_sources[0x55]	3314	1			T3	1		T5	2		T8	5
valid_sources[0x56]	3664	1			T3	2		T8	494		T9	15
valid_sources[0x57]	3707	1			T3	5		T8	7		T9	4
valid_sources[0x58]	7655	1			T3	3		T8	1047		T9	12
valid_sources[0x59]	3700	1			T3	3		T5	3		T8	253
valid_sources[0x5a]	6994	1			T3	1		T9	8		T10	34
valid_sources[0x5b]	3712	1			T3	2		T5	1		T9	21
valid_sources[0x5c]	3407	1			T3	4		T5	3		T9	15
valid_sources[0x5d]	8118	1			T5	4		T8	16		T9	7
valid_sources[0x5e]	8450	1			T1	3200		T3	2		T5	5
valid_sources[0x5f]	4642	1			T3	3		T8	142		T9	11
valid_sources[0x60]	3808	1			T3	1		T9	24		T10	38
valid_sources[0x61]	3101	1			T3	7		T5	2		T9	9
valid_sources[0x62]	3359	1			T3	14		T5	2		T9	13
valid_sources[0x63]	4304	1			T3	7		T5	2		T9	10
valid_sources[0x64]	3721	1			T5	6		T8	229		T9	12
valid_sources[0x65]	4110	1			T3	11		T8	3		T9	11
valid_sources[0x66]	4226	1			T3	6		T5	1		T8	148
valid_sources[0x67]	3747	1			T3	7		T5	1		T9	15
valid_sources[0x68]	4353	1			T3	3		T5	3		T8	298
valid_sources[0x69]	3467	1			T3	8		T9	19		T10	48
valid_sources[0x6a]	3401	1			T3	3		T6	1		T9	11
valid_sources[0x6b]	3116	1			T5	3		T9	11		T10	44
valid_sources[0x6c]	3472	1			T3	5		T5	10		T9	14
valid_sources[0x6d]	3226	1			T3	3		T9	15		T10	33
valid_sources[0x6e]	4132	1			T3	5		T5	5		T9	13
valid_sources[0x6f]	3213	1			T3	3		T5	1		T9	19
valid_sources[0x70]	4104	1			T5	4		T9	13		T10	35
valid_sources[0x71]	4001	1			T3	6		T6	2		T9	19
valid_sources[0x72]	3697	1			T3	6		T5	5		T9	20
valid_sources[0x73]	3649	1			T3	5		T9	8		T10	45
valid_sources[0x74]	3535	1			T3	1		T5	1		T8	65
valid_sources[0x75]	3532	1			T3	11		T9	8		T10	32
valid_sources[0x76]	3004	1			T3	5		T9	20		T10	33
valid_sources[0x77]	4498	1			T3	5		T9	11		T10	41
valid_sources[0x78]	5889	1			T3	3		T9	22		T10	53
valid_sources[0x79]	6794	1			T3	7		T5	7		T8	3
valid_sources[0x7a]	6590	1			T3	5		T8	91		T9	16
valid_sources[0x7b]	3321	1			T3	3		T9	11		T10	33
valid_sources[0x7c]	3883	1			T8	4		T9	6		T10	43
valid_sources[0x7d]	3766	1			T3	5		T8	11		T9	9
valid_sources[0x7e]	3220	1			T3	6		T9	10		T10	44
valid_sources[0x7f]	4607	1			T3	2		T8	484		T9	11
valid_sources[0x80]	3246	1			T3	4		T9	10		T10	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

259524

1

T1

679

T3

262

T5

92

values[0x0]

all_enables

biggest_size

84033

1

T1

286

T3

84

T5

32

values[0x1]

all_enables

biggest_size

45024

1

T1

139

T3

37

T5

19