Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T8
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T10
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T10
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13430233	14661	0	0
gen_assertions[0].RstEnOn_A	13430233	1143	0	0
gen_assertions[0].RstNOff_A	13430233	14661	0	0
gen_assertions[0].RstNOn_A	13430233	1143	0	0
gen_assertions[1].RstEnOff_A	53720625	13331	0	0
gen_assertions[1].RstEnOn_A	53720625	1122	0	0
gen_assertions[1].RstNOff_A	53720625	13331	0	0
gen_assertions[1].RstNOn_A	53720625	1122	0	0
gen_assertions[2].RstEnOff_A	26861463	13376	0	0
gen_assertions[2].RstEnOn_A	26861463	1102	0	0
gen_assertions[2].RstNOff_A	26861463	13376	0	0
gen_assertions[2].RstNOn_A	26861463	1102	0	0
gen_assertions[3].RstEnOff_A	26861608	13441	0	0
gen_assertions[3].RstEnOn_A	26861608	1169	0	0
gen_assertions[3].RstNOff_A	26861608	13441	0	0
gen_assertions[3].RstNOn_A	26861608	1169	0	0
gen_assertions[4].RstEnOff_A	1696659	22459	0	0
gen_assertions[4].RstEnOn_A	1696659	1195	0	0
gen_assertions[4].RstNOff_A	1696659	22459	0	0
gen_assertions[4].RstNOn_A	1696659	1195	0	0
gen_assertions[5].RstEnOff_A	13430233	14903	0	0
gen_assertions[5].RstEnOn_A	13430233	1250	0	0
gen_assertions[5].RstNOff_A	13430233	14903	0	0
gen_assertions[5].RstNOn_A	13430233	1250	0	0
gen_assertions[6].RstEnOff_A	13430233	14942	0	0
gen_assertions[6].RstEnOn_A	13430233	1300	0	0
gen_assertions[6].RstNOff_A	13430233	14942	0	0
gen_assertions[6].RstNOn_A	13430233	1300	0	0
gen_assertions[7].RstEnOff_A	13430233	15007	0	0
gen_assertions[7].RstEnOn_A	13430233	1350	0	0
gen_assertions[7].RstNOff_A	13430233	15007	0	0
gen_assertions[7].RstNOn_A	13430233	1350	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	14661	0	0
T1	56149	75	0	0
T2	5827	0	0	0
T3	12021	6	0	0
T4	5815	0	0	0
T5	2860	4	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	177	0	0
T9	29240	75	0	0
T10	78925	145	0	0
T11	0	4	0	0
T12	0	40	0	0
T13	0	4	0	0
T14	0	209	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	1143	0	0
T3	12021	6	0	0
T4	5815	0	0	0
T5	2860	0	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	13	0	0
T9	29240	0	0	0
T10	78925	17	0	0
T11	2845	0	0	0
T13	0	4	0	0
T14	0	24	0	0
T27	0	2	0	0
T29	0	14	0	0
T30	0	6	0	0
T56	1787	0	0	0
T58	0	5	0	0
T99	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	14661	0	0
T1	56149	75	0	0
T2	5827	0	0	0
T3	12021	6	0	0
T4	5815	0	0	0
T5	2860	4	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	177	0	0
T9	29240	75	0	0
T10	78925	145	0	0
T11	0	4	0	0
T12	0	40	0	0
T13	0	4	0	0
T14	0	209	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	1143	0	0
T3	12021	6	0	0
T4	5815	0	0	0
T5	2860	0	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	13	0	0
T9	29240	0	0	0
T10	78925	17	0	0
T11	2845	0	0	0
T13	0	4	0	0
T14	0	24	0	0
T27	0	2	0	0
T29	0	14	0	0
T30	0	6	0	0
T56	1787	0	0	0
T58	0	5	0	0
T99	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53720625	13331	0	0
T1	224553	66	0	0
T2	23327	0	0	0
T3	48084	7	0	0
T4	23262	0	0	0
T5	11452	2	0	0
T6	5651	0	0	0
T7	6577	0	0	0
T8	360414	162	0	0
T9	117010	70	0	0
T10	315682	130	0	0
T11	0	4	0	0
T12	0	33	0	0
T13	0	6	0	0
T14	0	193	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53720625	1122	0	0
T3	48084	7	0	0
T4	23262	0	0	0
T5	11452	0	0	0
T6	5651	0	0	0
T7	6577	0	0	0
T8	360414	12	0	0
T9	117010	0	0	0
T10	315682	18	0	0
T11	11382	1	0	0
T13	0	6	0	0
T14	0	29	0	0
T27	0	1	0	0
T29	0	11	0	0
T56	7154	0	0	0
T58	0	8	0	0
T99	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53720625	13331	0	0
T1	224553	66	0	0
T2	23327	0	0	0
T3	48084	7	0	0
T4	23262	0	0	0
T5	11452	2	0	0
T6	5651	0	0	0
T7	6577	0	0	0
T8	360414	162	0	0
T9	117010	70	0	0
T10	315682	130	0	0
T11	0	4	0	0
T12	0	33	0	0
T13	0	6	0	0
T14	0	193	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53720625	1122	0	0
T3	48084	7	0	0
T4	23262	0	0	0
T5	11452	0	0	0
T6	5651	0	0	0
T7	6577	0	0	0
T8	360414	12	0	0
T9	117010	0	0	0
T10	315682	18	0	0
T11	11382	1	0	0
T13	0	6	0	0
T14	0	29	0	0
T27	0	1	0	0
T29	0	11	0	0
T56	7154	0	0	0
T58	0	8	0	0
T99	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26861463	13376	0	0
T1	112298	66	0	0
T2	11661	0	0	0
T3	24043	5	0	0
T4	11627	0	0	0
T5	5722	2	0	0
T6	2824	0	0	0
T7	3287	0	0	0
T8	180175	163	0	0
T9	58494	70	0	0
T10	157831	132	0	0
T11	0	4	0	0
T12	0	33	0	0
T13	0	8	0	0
T14	0	192	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26861463	1102	0	0
T3	24043	5	0	0
T4	11627	0	0	0
T5	5722	0	0	0
T6	2824	0	0	0
T7	3287	0	0	0
T8	180175	11	0	0
T9	58494	0	0	0
T10	157831	17	0	0
T11	5688	1	0	0
T13	0	8	0	0
T14	0	28	0	0
T29	0	10	0	0
T30	0	8	0	0
T56	3577	0	0	0
T58	0	8	0	0
T100	0	9	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26861463	13376	0	0
T1	112298	66	0	0
T2	11661	0	0	0
T3	24043	5	0	0
T4	11627	0	0	0
T5	5722	2	0	0
T6	2824	0	0	0
T7	3287	0	0	0
T8	180175	163	0	0
T9	58494	70	0	0
T10	157831	132	0	0
T11	0	4	0	0
T12	0	33	0	0
T13	0	8	0	0
T14	0	192	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26861463	1102	0	0
T3	24043	5	0	0
T4	11627	0	0	0
T5	5722	0	0	0
T6	2824	0	0	0
T7	3287	0	0	0
T8	180175	11	0	0
T9	58494	0	0	0
T10	157831	17	0	0
T11	5688	1	0	0
T13	0	8	0	0
T14	0	28	0	0
T29	0	10	0	0
T30	0	8	0	0
T56	3577	0	0	0
T58	0	8	0	0
T100	0	9	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26861608	13441	0	0
T1	112299	66	0	0
T2	11662	0	0	0
T3	24042	9	0	0
T4	11631	0	0	0
T5	5726	2	0	0
T6	2825	0	0	0
T7	3288	0	0	0
T8	180195	162	0	0
T9	58490	70	0	0
T10	157837	130	0	0
T11	0	3	0	0
T12	0	33	0	0
T13	0	8	0	0
T14	0	193	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26861608	1169	0	0
T3	24042	9	0	0
T4	11631	0	0	0
T5	5726	0	0	0
T6	2825	0	0	0
T7	3288	0	0	0
T8	180195	10	0	0
T9	58490	0	0	0
T10	157837	15	0	0
T11	5692	0	0	0
T13	0	8	0	0
T14	0	30	0	0
T29	0	13	0	0
T30	0	10	0	0
T56	3577	0	0	0
T58	0	7	0	0
T100	0	11	0	0
T101	0	9	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26861608	13441	0	0
T1	112299	66	0	0
T2	11662	0	0	0
T3	24042	9	0	0
T4	11631	0	0	0
T5	5726	2	0	0
T6	2825	0	0	0
T7	3288	0	0	0
T8	180195	162	0	0
T9	58490	70	0	0
T10	157837	130	0	0
T11	0	3	0	0
T12	0	33	0	0
T13	0	8	0	0
T14	0	193	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26861608	1169	0	0
T3	24042	9	0	0
T4	11631	0	0	0
T5	5726	0	0	0
T6	2825	0	0	0
T7	3288	0	0	0
T8	180195	10	0	0
T9	58490	0	0	0
T10	157837	15	0	0
T11	5692	0	0	0
T13	0	8	0	0
T14	0	30	0	0
T29	0	13	0	0
T30	0	10	0	0
T56	3577	0	0	0
T58	0	7	0	0
T100	0	11	0	0
T101	0	9	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696659	22459	0	0
T1	7032	97	0	0
T2	732	3	0	0
T3	1501	10	0	0
T4	728	3	0	0
T5	357	6	0	0
T6	174	1	0	0
T7	204	1	0	0
T8	11543	240	0	0
T9	3671	74	0	0
T10	10071	208	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696659	1195	0	0
T3	1501	9	0	0
T4	728	0	0	0
T5	357	0	0	0
T6	174	0	0	0
T7	204	0	0	0
T8	11543	11	0	0
T9	3671	0	0	0
T10	10071	18	0	0
T11	355	1	0	0
T13	0	7	0	0
T14	0	27	0	0
T29	0	14	0	0
T30	0	9	0	0
T56	222	0	0	0
T58	0	7	0	0
T100	0	8	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696659	22459	0	0
T1	7032	97	0	0
T2	732	3	0	0
T3	1501	10	0	0
T4	728	3	0	0
T5	357	6	0	0
T6	174	1	0	0
T7	204	1	0	0
T8	11543	240	0	0
T9	3671	74	0	0
T10	10071	208	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696659	1195	0	0
T3	1501	9	0	0
T4	728	0	0	0
T5	357	0	0	0
T6	174	0	0	0
T7	204	0	0	0
T8	11543	11	0	0
T9	3671	0	0	0
T10	10071	18	0	0
T11	355	1	0	0
T13	0	7	0	0
T14	0	27	0	0
T29	0	14	0	0
T30	0	9	0	0
T56	222	0	0	0
T58	0	7	0	0
T100	0	8	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	14903	0	0
T1	56149	75	0	0
T2	5827	0	0	0
T3	12021	11	0	0
T4	5815	0	0	0
T5	2860	5	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	174	0	0
T9	29240	75	0	0
T10	78925	141	0	0
T11	0	4	0	0
T12	0	40	0	0
T13	0	9	0	0
T14	0	209	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	1250	0	0
T3	12021	11	0	0
T4	5815	0	0	0
T5	2860	1	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	11	0	0
T9	29240	0	0	0
T10	78925	15	0	0
T11	2845	0	0	0
T13	0	9	0	0
T14	0	25	0	0
T29	0	14	0	0
T30	0	11	0	0
T56	1787	0	0	0
T58	0	10	0	0
T100	0	14	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	14903	0	0
T1	56149	75	0	0
T2	5827	0	0	0
T3	12021	11	0	0
T4	5815	0	0	0
T5	2860	5	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	174	0	0
T9	29240	75	0	0
T10	78925	141	0	0
T11	0	4	0	0
T12	0	40	0	0
T13	0	9	0	0
T14	0	209	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	1250	0	0
T3	12021	11	0	0
T4	5815	0	0	0
T5	2860	1	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	11	0	0
T9	29240	0	0	0
T10	78925	15	0	0
T11	2845	0	0	0
T13	0	9	0	0
T14	0	25	0	0
T29	0	14	0	0
T30	0	11	0	0
T56	1787	0	0	0
T58	0	10	0	0
T100	0	14	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	14942	0	0
T1	56149	75	0	0
T2	5827	0	0	0
T3	12021	10	0	0
T4	5815	0	0	0
T5	2860	4	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	172	0	0
T9	29240	75	0	0
T10	78925	146	0	0
T11	0	4	0	0
T12	0	40	0	0
T13	0	11	0	0
T14	0	209	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	1300	0	0
T3	12021	10	0	0
T4	5815	0	0	0
T5	2860	0	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	9	0	0
T9	29240	0	0	0
T10	78925	19	0	0
T11	2845	0	0	0
T13	0	11	0	0
T14	0	26	0	0
T29	0	14	0	0
T30	0	10	0	0
T56	1787	0	0	0
T58	0	12	0	0
T100	0	12	0	0
T101	0	13	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	14942	0	0
T1	56149	75	0	0
T2	5827	0	0	0
T3	12021	10	0	0
T4	5815	0	0	0
T5	2860	4	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	172	0	0
T9	29240	75	0	0
T10	78925	146	0	0
T11	0	4	0	0
T12	0	40	0	0
T13	0	11	0	0
T14	0	209	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	1300	0	0
T3	12021	10	0	0
T4	5815	0	0	0
T5	2860	0	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	9	0	0
T9	29240	0	0	0
T10	78925	19	0	0
T11	2845	0	0	0
T13	0	11	0	0
T14	0	26	0	0
T29	0	14	0	0
T30	0	10	0	0
T56	1787	0	0	0
T58	0	12	0	0
T100	0	12	0	0
T101	0	13	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	15007	0	0
T1	56149	75	0	0
T2	5827	0	0	0
T3	12021	13	0	0
T4	5815	0	0	0
T5	2860	4	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	171	0	0
T9	29240	75	0	0
T10	78925	145	0	0
T11	0	4	0	0
T12	0	40	0	0
T13	0	12	0	0
T14	0	208	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	1350	0	0
T3	12021	13	0	0
T4	5815	0	0	0
T5	2860	0	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	7	0	0
T9	29240	0	0	0
T10	78925	18	0	0
T11	2845	0	0	0
T13	0	12	0	0
T14	0	23	0	0
T29	0	13	0	0
T30	0	14	0	0
T56	1787	0	0	0
T58	0	13	0	0
T100	0	11	0	0
T102	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	15007	0	0
T1	56149	75	0	0
T2	5827	0	0	0
T3	12021	13	0	0
T4	5815	0	0	0
T5	2860	4	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	171	0	0
T9	29240	75	0	0
T10	78925	145	0	0
T11	0	4	0	0
T12	0	40	0	0
T13	0	12	0	0
T14	0	208	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	1350	0	0
T3	12021	13	0	0
T4	5815	0	0	0
T5	2860	0	0	0
T6	1412	0	0	0
T7	1643	0	0	0
T8	90094	7	0	0
T9	29240	0	0	0
T10	78925	18	0	0
T11	2845	0	0	0
T13	0	12	0	0
T14	0	23	0	0
T29	0	13	0	0
T30	0	14	0	0
T56	1787	0	0	0
T58	0	13	0	0
T100	0	11	0	0
T102	0	1	0	0