Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12603054	6832	0	0
alert_regwen_rd_A	12603054	4883	0	0
cpu_regwen_rd_A	12603054	5121	0	0
sw_rst_ctrl_n_0_rd_A	12603054	8999	0	0
sw_rst_ctrl_n_1_rd_A	12603054	9008	0	0
sw_rst_ctrl_n_2_rd_A	12603054	9078	0	0
sw_rst_ctrl_n_3_rd_A	12603054	9027	0	0
sw_rst_ctrl_n_4_rd_A	12603054	9182	0	0
sw_rst_ctrl_n_5_rd_A	12603054	9205	0	0
sw_rst_ctrl_n_6_rd_A	12603054	9136	0	0
sw_rst_ctrl_n_7_rd_A	12603054	8994	0	0
sw_rst_regwen_0_rd_A	12603054	5585	0	0
sw_rst_regwen_1_rd_A	12603054	5627	0	0
sw_rst_regwen_2_rd_A	12603054	5388	0	0
sw_rst_regwen_3_rd_A	12603054	5489	0	0
sw_rst_regwen_4_rd_A	12603054	5432	0	0
sw_rst_regwen_5_rd_A	12603054	5530	0	0
sw_rst_regwen_6_rd_A	12603054	5564	0	0
sw_rst_regwen_7_rd_A	12603054	5469	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	6832	0	0
T63	2436	6	0	0
T64	2376	16	0	0
T65	10675	1	0	0
T66	7021	387	0	0
T68	17854	3	0	0
T83	10041	421	0	0
T86	17226	1	0	0
T95	3866	69	0	0
T96	3193	14	0	0
T97	20358	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	4883	0	0
T14	219249	297	0	0
T15	15890	0	0	0
T16	27417	0	0	0
T32	0	61	0	0
T50	1674	0	0	0
T51	4147	0	0	0
T52	1655	0	0	0
T57	5315	0	0	0
T58	8008	0	0	0
T105	0	32	0	0
T106	0	57	0	0
T111	0	57	0	0
T122	0	37	0	0
T123	0	39	0	0
T124	0	533	0	0
T125	0	33	0	0
T126	0	54	0	0
T127	1795	0	0	0
T128	5469	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	5121	0	0
T14	219249	326	0	0
T15	15890	0	0	0
T16	27417	0	0	0
T32	0	79	0	0
T50	1674	0	0	0
T51	4147	0	0	0
T52	1655	0	0	0
T57	5315	0	0	0
T58	8008	0	0	0
T105	0	41	0	0
T106	0	55	0	0
T111	0	52	0	0
T122	0	30	0	0
T123	0	41	0	0
T124	0	611	0	0
T125	0	26	0	0
T126	0	72	0	0
T127	1795	0	0	0
T128	5469	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	8999	0	0
T3	11978	149	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	178	0	0
T14	0	662	0	0
T32	0	92	0	0
T56	1769	0	0	0
T105	0	42	0	0
T106	0	42	0	0
T122	0	47	0	0
T129	0	31	0	0
T130	0	78	0	0
T131	0	62	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	9008	0	0
T3	11978	175	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	183	0	0
T14	0	719	0	0
T32	0	62	0	0
T56	1769	0	0	0
T105	0	45	0	0
T106	0	69	0	0
T122	0	44	0	0
T129	0	35	0	0
T130	0	71	0	0
T131	0	52	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	9078	0	0
T3	11978	179	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	190	0	0
T14	0	678	0	0
T32	0	56	0	0
T56	1769	0	0	0
T105	0	53	0	0
T106	0	41	0	0
T122	0	31	0	0
T129	0	42	0	0
T130	0	61	0	0
T131	0	41	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	9027	0	0
T3	11978	205	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	131	0	0
T14	0	672	0	0
T32	0	68	0	0
T56	1769	0	0	0
T105	0	37	0	0
T106	0	72	0	0
T122	0	40	0	0
T129	0	42	0	0
T130	0	83	0	0
T131	0	64	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	9182	0	0
T3	11978	177	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	190	0	0
T14	0	683	0	0
T32	0	60	0	0
T56	1769	0	0	0
T105	0	44	0	0
T106	0	56	0	0
T122	0	41	0	0
T129	0	52	0	0
T130	0	57	0	0
T131	0	61	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	9205	0	0
T3	11978	243	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	180	0	0
T14	0	706	0	0
T32	0	107	0	0
T56	1769	0	0	0
T105	0	46	0	0
T106	0	37	0	0
T122	0	44	0	0
T129	0	48	0	0
T130	0	90	0	0
T131	0	65	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	9136	0	0
T3	11978	174	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	195	0	0
T14	0	665	0	0
T32	0	88	0	0
T56	1769	0	0	0
T105	0	53	0	0
T106	0	47	0	0
T122	0	50	0	0
T129	0	32	0	0
T130	0	74	0	0
T131	0	62	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	8994	0	0
T3	11978	157	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	169	0	0
T14	0	711	0	0
T32	0	73	0	0
T56	1769	0	0	0
T105	0	74	0	0
T106	0	79	0	0
T122	0	34	0	0
T129	0	42	0	0
T130	0	54	0	0
T131	0	57	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	5585	0	0
T3	11978	26	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	26	0	0
T14	0	275	0	0
T32	0	73	0	0
T56	1769	0	0	0
T105	0	53	0	0
T106	0	38	0	0
T111	0	51	0	0
T122	0	40	0	0
T123	0	40	0	0
T132	0	3	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	5627	0	0
T3	11978	39	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	32	0	0
T14	0	319	0	0
T32	0	71	0	0
T56	1769	0	0	0
T105	0	54	0	0
T106	0	67	0	0
T111	0	57	0	0
T122	0	42	0	0
T123	0	37	0	0
T132	0	5	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	5388	0	0
T3	11978	20	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	51	0	0
T14	0	312	0	0
T32	0	59	0	0
T56	1769	0	0	0
T105	0	41	0	0
T106	0	39	0	0
T111	0	59	0	0
T122	0	29	0	0
T123	0	43	0	0
T132	0	6	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	5489	0	0
T3	11978	31	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	33	0	0
T14	0	317	0	0
T32	0	57	0	0
T56	1769	0	0	0
T105	0	44	0	0
T106	0	58	0	0
T111	0	61	0	0
T122	0	46	0	0
T123	0	21	0	0
T132	0	4	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	5432	0	0
T3	11978	17	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	31	0	0
T14	0	300	0	0
T32	0	81	0	0
T56	1769	0	0	0
T105	0	44	0	0
T106	0	39	0	0
T111	0	47	0	0
T122	0	43	0	0
T123	0	35	0	0
T132	0	13	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	5530	0	0
T3	11978	31	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	35	0	0
T14	0	306	0	0
T32	0	72	0	0
T56	1769	0	0	0
T105	0	47	0	0
T106	0	70	0	0
T111	0	69	0	0
T122	0	58	0	0
T123	0	43	0	0
T132	0	5	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	5564	0	0
T3	11978	38	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	30	0	0
T14	0	314	0	0
T32	0	100	0	0
T56	1769	0	0	0
T105	0	45	0	0
T106	0	46	0	0
T111	0	34	0	0
T122	0	41	0	0
T123	0	33	0	0
T132	0	6	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12603054	5469	0	0
T3	11978	45	0	0
T4	5078	0	0	0
T5	2572	0	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	0	0	0
T9	26182	0	0	0
T10	63183	0	0	0
T11	2603	0	0	0
T13	0	23	0	0
T14	0	308	0	0
T32	0	85	0	0
T56	1769	0	0	0
T105	0	39	0	0
T106	0	33	0	0
T111	0	48	0	0
T122	0	43	0	0
T123	0	49	0	0
T132	0	2	0	0