Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11876580	13699	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11876580	126508	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11876580	7052261	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11876580	201298	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11876580	13699	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11876580	126508	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11876580	7052261	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11876580	201298	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	13699	0	0
T1	53110	75	0	0
T2	5285	0	0	0
T3	11978	0	0	0
T4	5078	0	0	0
T5	2572	4	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	165	0	0
T9	26182	75	0	0
T10	63183	129	0	0
T11	0	4	0	0
T12	0	40	0	0
T14	0	185	0	0
T15	0	27	0	0
T16	0	46	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	126508	0	0
T1	53110	707	0	0
T2	5285	0	0	0
T3	11978	0	0	0
T4	5078	0	0	0
T5	2572	38	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	1526	0	0
T9	26182	717	0	0
T10	63183	1169	0	0
T11	0	38	0	0
T12	0	360	0	0
T14	0	1690	0	0
T15	0	243	0	0
T16	0	414	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	7052261	0	0
T1	53110	35663	0	0
T2	5285	572	0	0
T3	11978	11358	0	0
T4	5078	566	0	0
T5	2572	1642	0	0
T6	1393	742	0	0
T7	1553	980	0	0
T8	70220	36240	0	0
T9	26182	8727	0	0
T10	63183	33723	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	201298	0	0
T1	53110	1113	0	0
T2	5285	0	0	0
T3	11978	0	0	0
T4	5078	0	0	0
T5	2572	52	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	2426	0	0
T9	26182	1118	0	0
T10	63183	1874	0	0
T11	0	59	0	0
T12	0	554	0	0
T14	0	2697	0	0
T15	0	392	0	0
T16	0	688	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	13699	0	0
T1	53110	75	0	0
T2	5285	0	0	0
T3	11978	0	0	0
T4	5078	0	0	0
T5	2572	4	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	165	0	0
T9	26182	75	0	0
T10	63183	129	0	0
T11	0	4	0	0
T12	0	40	0	0
T14	0	185	0	0
T15	0	27	0	0
T16	0	46	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	126508	0	0
T1	53110	707	0	0
T2	5285	0	0	0
T3	11978	0	0	0
T4	5078	0	0	0
T5	2572	38	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	1526	0	0
T9	26182	717	0	0
T10	63183	1169	0	0
T11	0	38	0	0
T12	0	360	0	0
T14	0	1690	0	0
T15	0	243	0	0
T16	0	414	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	7052261	0	0
T1	53110	35663	0	0
T2	5285	572	0	0
T3	11978	11358	0	0
T4	5078	566	0	0
T5	2572	1642	0	0
T6	1393	742	0	0
T7	1553	980	0	0
T8	70220	36240	0	0
T9	26182	8727	0	0
T10	63183	33723	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	201298	0	0
T1	53110	1113	0	0
T2	5285	0	0	0
T3	11978	0	0	0
T4	5078	0	0	0
T5	2572	52	0	0
T6	1393	0	0	0
T7	1553	0	0	0
T8	70220	2426	0	0
T9	26182	1118	0	0
T10	63183	1874	0	0
T11	0	59	0	0
T12	0	554	0	0
T14	0	2697	0	0
T15	0	392	0	0
T16	0	688	0	0