Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T10
0	1	Covered	T8,T10,T11
1	0	Covered	T5,T8,T10

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T5,T8,T10
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55961019	8977	0	0
CascadeEffAonToRstPorAboveRise_A	55961019	8977	0	0
CascadeEffAonToRstPorIoAboveFall_A	53720625	8977	0	0
CascadeEffAonToRstPorIoAboveRise_A	53720625	8977	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26861463	8977	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26861463	8977	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13430233	8977	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13430233	8977	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26861608	8977	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26861608	8977	0	0
CascadeLcToLcAboveFall_A	55961019	22676	0	0
CascadeLcToLcAboveRise_A	55961019	22676	0	0
CascadeLcToLcAonAboveFall_A	1696659	22676	0	0
CascadeLcToLcAonAboveRise_A	1696659	22676	0	0
CascadeLcToLcShadowedAboveFall_A	55961019	22676	0	0
CascadeLcToLcShadowedAboveRise_A	55961019	22676	0	0
CascadePorToAonAboveFall_A	1696659	7063	0	0
CascadeSysToSysAboveFall_A	55961019	22676	0	0
CascadeSysToSysAboveRise_A	55961019	22676	0	0
ScanRstToAonRise_A	1696659	220	0	0
StablePorToAonRise_A	1696659	8977	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11876580	22676	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11876580	22676	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11876580	22676	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11876580	22676	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13430233	22676	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13430233	22676	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11876580	22676	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11876580	22676	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11876580	22676	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11876580	22676	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55961019	8977	0	0
T1	233938	27	0	0
T2	24302	8	0	0
T3	50090	1	0	0
T4	24233	8	0	0
T5	11929	2	0	0
T6	5887	1	0	0
T7	6851	1	0	0
T8	375382	71	0	0
T9	121872	27	0	0
T10	328842	65	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55961019	8977	0	0
T1	233938	27	0	0
T2	24302	8	0	0
T3	50090	1	0	0
T4	24233	8	0	0
T5	11929	2	0	0
T6	5887	1	0	0
T7	6851	1	0	0
T8	375382	71	0	0
T9	121872	27	0	0
T10	328842	65	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53720625	8977	0	0
T1	224553	27	0	0
T2	23327	8	0	0
T3	48084	1	0	0
T4	23262	8	0	0
T5	11452	2	0	0
T6	5651	1	0	0
T7	6577	1	0	0
T8	360414	71	0	0
T9	117010	27	0	0
T10	315682	65	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53720625	8977	0	0
T1	224553	27	0	0
T2	23327	8	0	0
T3	48084	1	0	0
T4	23262	8	0	0
T5	11452	2	0	0
T6	5651	1	0	0
T7	6577	1	0	0
T8	360414	71	0	0
T9	117010	27	0	0
T10	315682	65	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26861463	8977	0	0
T1	112298	27	0	0
T2	11661	8	0	0
T3	24043	1	0	0
T4	11627	8	0	0
T5	5722	2	0	0
T6	2824	1	0	0
T7	3287	1	0	0
T8	180175	71	0	0
T9	58494	27	0	0
T10	157831	65	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26861463	8977	0	0
T1	112298	27	0	0
T2	11661	8	0	0
T3	24043	1	0	0
T4	11627	8	0	0
T5	5722	2	0	0
T6	2824	1	0	0
T7	3287	1	0	0
T8	180175	71	0	0
T9	58494	27	0	0
T10	157831	65	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	8977	0	0
T1	56149	27	0	0
T2	5827	8	0	0
T3	12021	1	0	0
T4	5815	8	0	0
T5	2860	2	0	0
T6	1412	1	0	0
T7	1643	1	0	0
T8	90094	71	0	0
T9	29240	27	0	0
T10	78925	65	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	8977	0	0
T1	56149	27	0	0
T2	5827	8	0	0
T3	12021	1	0	0
T4	5815	8	0	0
T5	2860	2	0	0
T6	1412	1	0	0
T7	1643	1	0	0
T8	90094	71	0	0
T9	29240	27	0	0
T10	78925	65	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26861608	8977	0	0
T1	112299	27	0	0
T2	11662	8	0	0
T3	24042	1	0	0
T4	11631	8	0	0
T5	5726	2	0	0
T6	2825	1	0	0
T7	3288	1	0	0
T8	180195	71	0	0
T9	58490	27	0	0
T10	157837	65	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26861608	8977	0	0
T1	112299	27	0	0
T2	11662	8	0	0
T3	24042	1	0	0
T4	11631	8	0	0
T5	5726	2	0	0
T6	2825	1	0	0
T7	3288	1	0	0
T8	180195	71	0	0
T9	58490	27	0	0
T10	157837	65	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55961019	22676	0	0
T1	233938	102	0	0
T2	24302	8	0	0
T3	50090	1	0	0
T4	24233	8	0	0
T5	11929	6	0	0
T6	5887	1	0	0
T7	6851	1	0	0
T8	375382	236	0	0
T9	121872	102	0	0
T10	328842	194	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55961019	22676	0	0
T1	233938	102	0	0
T2	24302	8	0	0
T3	50090	1	0	0
T4	24233	8	0	0
T5	11929	6	0	0
T6	5887	1	0	0
T7	6851	1	0	0
T8	375382	236	0	0
T9	121872	102	0	0
T10	328842	194	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696659	22676	0	0
T1	7032	102	0	0
T2	732	8	0	0
T3	1501	1	0	0
T4	728	8	0	0
T5	357	6	0	0
T6	174	1	0	0
T7	204	1	0	0
T8	11543	236	0	0
T9	3671	102	0	0
T10	10071	194	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696659	22676	0	0
T1	7032	102	0	0
T2	732	8	0	0
T3	1501	1	0	0
T4	728	8	0	0
T5	357	6	0	0
T6	174	1	0	0
T7	204	1	0	0
T8	11543	236	0	0
T9	3671	102	0	0
T10	10071	194	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55961019	22676	0	0
T1	233938	102	0	0
T2	24302	8	0	0
T3	50090	1	0	0
T4	24233	8	0	0
T5	11929	6	0	0
T6	5887	1	0	0
T7	6851	1	0	0
T8	375382	236	0	0
T9	121872	102	0	0
T10	328842	194	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55961019	22676	0	0
T1	233938	102	0	0
T2	24302	8	0	0
T3	50090	1	0	0
T4	24233	8	0	0
T5	11929	6	0	0
T6	5887	1	0	0
T7	6851	1	0	0
T8	375382	236	0	0
T9	121872	102	0	0
T10	328842	194	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696659	7063	0	0
T1	7032	27	0	0
T2	732	8	0	0
T3	1501	1	0	0
T4	728	8	0	0
T5	357	1	0	0
T6	174	1	0	0
T7	204	1	0	0
T8	11543	40	0	0
T9	3671	27	0	0
T10	10071	31	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55961019	22676	0	0
T1	233938	102	0	0
T2	24302	8	0	0
T3	50090	1	0	0
T4	24233	8	0	0
T5	11929	6	0	0
T6	5887	1	0	0
T7	6851	1	0	0
T8	375382	236	0	0
T9	121872	102	0	0
T10	328842	194	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55961019	22676	0	0
T1	233938	102	0	0
T2	24302	8	0	0
T3	50090	1	0	0
T4	24233	8	0	0
T5	11929	6	0	0
T6	5887	1	0	0
T7	6851	1	0	0
T8	375382	236	0	0
T9	121872	102	0	0
T10	328842	194	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696659	220	0	0
T8	11543	1	0	0
T9	3671	0	0	0
T10	10071	8	0	0
T11	355	0	0	0
T12	3330	1	0	0
T13	1444	0	0	0
T14	30764	2	0	0
T16	0	1	0	0
T29	0	3	0	0
T32	0	1	0	0
T50	220	0	0	0
T56	222	0	0	0
T57	734	0	0	0
T105	0	1	0	0
T106	0	1	0	0
T133	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1696659	8977	0	0
T1	7032	27	0	0
T2	732	8	0	0
T3	1501	1	0	0
T4	728	8	0	0
T5	357	2	0	0
T6	174	1	0	0
T7	204	1	0	0
T8	11543	71	0	0
T9	3671	27	0	0
T10	10071	65	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	22676	0	0
T1	53110	102	0	0
T2	5285	8	0	0
T3	11978	1	0	0
T4	5078	8	0	0
T5	2572	6	0	0
T6	1393	1	0	0
T7	1553	1	0	0
T8	70220	236	0	0
T9	26182	102	0	0
T10	63183	194	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	22676	0	0
T1	53110	102	0	0
T2	5285	8	0	0
T3	11978	1	0	0
T4	5078	8	0	0
T5	2572	6	0	0
T6	1393	1	0	0
T7	1553	1	0	0
T8	70220	236	0	0
T9	26182	102	0	0
T10	63183	194	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	22676	0	0
T1	53110	102	0	0
T2	5285	8	0	0
T3	11978	1	0	0
T4	5078	8	0	0
T5	2572	6	0	0
T6	1393	1	0	0
T7	1553	1	0	0
T8	70220	236	0	0
T9	26182	102	0	0
T10	63183	194	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	22676	0	0
T1	53110	102	0	0
T2	5285	8	0	0
T3	11978	1	0	0
T4	5078	8	0	0
T5	2572	6	0	0
T6	1393	1	0	0
T7	1553	1	0	0
T8	70220	236	0	0
T9	26182	102	0	0
T10	63183	194	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	22676	0	0
T1	56149	102	0	0
T2	5827	8	0	0
T3	12021	1	0	0
T4	5815	8	0	0
T5	2860	6	0	0
T6	1412	1	0	0
T7	1643	1	0	0
T8	90094	236	0	0
T9	29240	102	0	0
T10	78925	194	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13430233	22676	0	0
T1	56149	102	0	0
T2	5827	8	0	0
T3	12021	1	0	0
T4	5815	8	0	0
T5	2860	6	0	0
T6	1412	1	0	0
T7	1643	1	0	0
T8	90094	236	0	0
T9	29240	102	0	0
T10	78925	194	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	22676	0	0
T1	53110	102	0	0
T2	5285	8	0	0
T3	11978	1	0	0
T4	5078	8	0	0
T5	2572	6	0	0
T6	1393	1	0	0
T7	1553	1	0	0
T8	70220	236	0	0
T9	26182	102	0	0
T10	63183	194	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	22676	0	0
T1	53110	102	0	0
T2	5285	8	0	0
T3	11978	1	0	0
T4	5078	8	0	0
T5	2572	6	0	0
T6	1393	1	0	0
T7	1553	1	0	0
T8	70220	236	0	0
T9	26182	102	0	0
T10	63183	194	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	22676	0	0
T1	53110	102	0	0
T2	5285	8	0	0
T3	11978	1	0	0
T4	5078	8	0	0
T5	2572	6	0	0
T6	1393	1	0	0
T7	1553	1	0	0
T8	70220	236	0	0
T9	26182	102	0	0
T10	63183	194	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876580	22676	0	0
T1	53110	102	0	0
T2	5285	8	0	0
T3	11978	1	0	0
T4	5078	8	0	0
T5	2572	6	0	0
T6	1393	1	0	0
T7	1553	1	0	0
T8	70220	236	0	0
T9	26182	102	0	0
T10	63183	194	0	0