RSTMGR Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: 2723ca659d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.640s 249.152us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.940s 148.706us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.950s 79.356us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 9.490s 2.305ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.400s 359.280us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.590s 170.113us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.950s 79.356us 20 20 100.00
rstmgr_csr_aliasing 2.400s 359.280us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.090s 197.691us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 3.120s 518.153us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.540s 276.867us 50 50 100.00
V2 reset_info rstmgr_reset 8.220s 1.988ms 50 50 100.00
V2 cpu_info rstmgr_reset 8.220s 1.988ms 50 50 100.00
V2 alert_info rstmgr_reset 8.220s 1.988ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 8.220s 1.988ms 50 50 100.00
V2 stress_all rstmgr_stress_all 1.064m 16.861ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.930s 89.449us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.720s 592.664us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.720s 592.664us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.940s 148.706us 5 5 100.00
rstmgr_csr_rw 0.950s 79.356us 20 20 100.00
rstmgr_csr_aliasing 2.400s 359.280us 5 5 100.00
rstmgr_same_csr_outstanding 1.690s 285.612us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.940s 148.706us 5 5 100.00
rstmgr_csr_rw 0.950s 79.356us 20 20 100.00
rstmgr_csr_aliasing 2.400s 359.280us 5 5 100.00
rstmgr_same_csr_outstanding 1.690s 285.612us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 26.920s 17.019ms 5 5 100.00
rstmgr_tl_intg_err 3.590s 1.425ms 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 26.920s 17.019ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 26.920s 17.019ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.590s 1.425ms 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.300s 181.858us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.020s 2.355ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.240s 243.986us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 26.920s 17.019ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.950s 79.356us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.950s 79.356us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.43 99.40 99.24 99.88 -- 99.83 99.46 98.77

Past Results